fix(margin): Reference VNOM to what the rails run at, and split profiles per CONN
86 of the 144 margin channels moved up +0.8% .. +2.5% to the measured
median for this platform (3.3 -> 3.38, 0.9 -> 0.915, 0.8 -> 0.82, ...).
That is not a display change. VNOM is the denominator of margin_status'
deviation %, and it is also the basis margin_set derives high/low/OV/UV
from - so both the number you read and the voltage you apply move with
it. A rail steady at 0.756 V used to read +0.80% against a nominal 0.75
and now reads 0.00%. Margin logs from before and after cannot be
compared: the reference moved, the hardware did not.
comboA/comboB are replaced by combo_SWB_CONN13..16_{high,low}. The
per-channel percentages are positional, so they follow the rails of one
specific board - applying a CONN13 profile to a CONN16 margins the wrong
rails and nothing detects it. SWB0 and SWB1 share a profile per CONN
because their rails are identical.
Fixes two things the deletion broke:
- margin_apply_profile_all.sh still named comboA for all nine boards,
which would now stop at "Profile not found" nine times over. It names
the matching per-CONN profile instead, with CB on the generic
combo_high3, and a note that the low pass is _high -> _low.
- docs/LTC2980_channel_map.csv is generated from settings/*.conf, so
all 86 changed rails were stale in it. Regenerated.
The eight new profiles also still carried comboA's header comment
("alternating high/low"), which describes neither what they contain nor
what they are for.
Script A -> V1.1.3.
Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_014RetWKFZFG1ZHcitQAyhwM
This commit is contained in:
Claude Opus 5
@@ -6,7 +6,7 @@ CB,CONN13,CH3,V1P8_ALW,1.8
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CB,CONN13,CH4,PWR_APU_VDDIO_SUS,1.1
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CB,CONN13,CH5,PWR_VDD_MISC_RUN,0.75
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CB,CONN13,CH6,PWR_APU_VDD_MEM_RUN,0.78
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CB,CONN13,CH7,V0P8_PHY2_DVDD,0.8
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CB,CONN13,CH7,V0P8_PHY2_DVDD,0.816
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CB,CONN13,CH8,V0P8_AVDD,0.8
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CB,CONN13,CH9,V0P8_PHY,0.8
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CB,CONN13,CH10,V1P8_FPGA,1.8
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@@ -14,132 +14,132 @@ CB,CONN13,CH11,V2P5_FPGA,2.5
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CB,CONN13,CH12,V1P1_FPGA,1.1
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CB,CONN13,CH13,P5V_STBY,5.0
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CB,CONN13,CH14,P3V3_STBY,3.3
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CB,CONN13,CH15,V0P8_PHY2_AVDD,0.8
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CB,CONN13,CH15,V0P8_PHY2_AVDD,0.816
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SWB0,CONN13,CH0,P0V75_DVDD_47,0.75
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SWB0,CONN13,CH1,P0V75_AVDD_47,0.75
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SWB0,CONN13,CH2,P1V5_AVDD_47,1.5
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SWB0,CONN13,CH3,P0V9_AVDD_47,0.9
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SWB0,CONN13,CH4,P1V8_1,1.8
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SWB0,CONN13,CH5,PVDD3_3V_SYNTH_LDO_A3,3.3
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SWB0,CONN13,CH6,PVDD3_3V_SYNTH_LDO_B1,3.3
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SWB0,CONN13,CH7,P1V8_3,1.8
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SWB0,CONN13,CH1,P0V75_AVDD_47,0.756
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SWB0,CONN13,CH2,P1V5_AVDD_47,1.524
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SWB0,CONN13,CH3,P0V9_AVDD_47,0.915
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SWB0,CONN13,CH4,P1V8_1,1.816
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SWB0,CONN13,CH5,PVDD3_3V_SYNTH_LDO_A3,3.38
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SWB0,CONN13,CH6,PVDD3_3V_SYNTH_LDO_B1,3.38
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SWB0,CONN13,CH7,P1V8_3,1.816
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SWB0,CONN13,CH8,P1V8_DVDDIO_3,1.8
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SWB0,CONN13,CH9,P0V75_DVDD_39,0.75
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SWB0,CONN13,CH10,P0V75_AVDD_39,0.75
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SWB0,CONN13,CH11,P1V5_AVDD_39,1.5
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SWB0,CONN13,CH12,P0V9_AVDD_39,0.9
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SWB0,CONN13,CH10,P0V75_AVDD_39,0.756
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SWB0,CONN13,CH11,P1V5_AVDD_39,1.524
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SWB0,CONN13,CH12,P0V9_AVDD_39,0.915
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SWB0,CONN13,CH13,PVDD1V5_2,1.5
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SWB0,CONN13,CH14,PVDD1V8_DUT,1.8
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SWB0,CONN13,CH15,PVDD_MDIO,1.2
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SWB0,CONN14,CH0,P0V75_AVDD_7,0.75
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SWB0,CONN14,CH1,P1V5_AVDD_7,1.5
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SWB0,CONN14,CH2,P0V9_AVDD_7,0.9
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SWB0,CONN14,CH3,P1V8_5,1.8
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SWB0,CONN14,CH4,P1V8_2,1.8
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SWB0,CONN14,CH5,PVDD3_3V_SYNTH_LDO_B2,3.3
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SWB0,CONN14,CH6,PVDD3_3V_SYNTH_LDO_A2,3.3
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SWB0,CONN14,CH7,PVDD3_3V_SYNTH_LDO_A1,3.3
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SWB0,CONN14,CH8,PVDD1V5_TSC,1.5
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SWB0,CONN14,CH9,PVDD1V5_ANLG,1.5
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SWB0,CONN14,CH0,P0V75_AVDD_7,0.756
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SWB0,CONN14,CH1,P1V5_AVDD_7,1.524
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SWB0,CONN14,CH2,P0V9_AVDD_7,0.915
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SWB0,CONN14,CH3,P1V8_5,1.816
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SWB0,CONN14,CH4,P1V8_2,1.816
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SWB0,CONN14,CH5,PVDD3_3V_SYNTH_LDO_B2,3.38
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SWB0,CONN14,CH6,PVDD3_3V_SYNTH_LDO_A2,3.38
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SWB0,CONN14,CH7,PVDD3_3V_SYNTH_LDO_A1,3.38
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SWB0,CONN14,CH8,PVDD1V5_TSC,1.516
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SWB0,CONN14,CH9,PVDD1V5_ANLG,1.516
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SWB0,CONN14,CH10,NC,-
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SWB0,CONN14,CH11,NC,-
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SWB0,CONN14,CH12,PVDD1V5_1,1.5
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SWB0,CONN14,CH13,NC,-
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SWB0,CONN14,CH14,P1V8_DVDDIO_1,1.8
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SWB0,CONN14,CH15,P0V75_DVDD_7,0.75
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SWB0,CONN15,CH0,P1V5_AVDD_55,1.5
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SWB0,CONN15,CH1,P0V9_AVDD_55,0.9
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SWB0,CONN15,CH0,P1V5_AVDD_55,1.524
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SWB0,CONN15,CH1,P0V9_AVDD_55,0.915
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SWB0,CONN15,CH2,P0V75_DVDD_63,0.75
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SWB0,CONN15,CH3,P0V75_AVDD_63,0.75
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SWB0,CONN15,CH4,P1V5_AVDD_63,1.5
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SWB0,CONN15,CH5,P0V9_AVDD_63,0.9
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SWB0,CONN15,CH6,PVDD3_3V_SYNTH_LDO_B3,3.3
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SWB0,CONN15,CH3,P0V75_AVDD_63,0.756
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SWB0,CONN15,CH4,P1V5_AVDD_63,1.524
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SWB0,CONN15,CH5,P0V9_AVDD_63,0.915
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SWB0,CONN15,CH6,PVDD3_3V_SYNTH_LDO_B3,3.38
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SWB0,CONN15,CH7,PVDD1V5_3,1.5
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SWB0,CONN15,CH8,P0V85_STBY,0.85
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SWB0,CONN15,CH9,P1V8_STBY,1.8
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SWB0,CONN15,CH10,NC,-
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SWB0,CONN15,CH11,P3V3_STBY,3.3
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SWB0,CONN15,CH12,PVDD0V9_2,0.9
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SWB0,CONN15,CH12,PVDD0V9_2,0.91
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SWB0,CONN15,CH13,P0V75_DVDD_55,0.75
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SWB0,CONN15,CH14,P0V75_AVDD_55,0.75
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SWB0,CONN15,CH14,P0V75_AVDD_55,0.756
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SWB0,CONN15,CH15,P1V8_DVDDIO_4,1.8
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SWB0,CONN16,CH0,PVDD1V5_0,1.5
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SWB0,CONN16,CH1,P1V8_4,1.8
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SWB0,CONN16,CH2,PVDD3_3V_SYNTH_LDO_B5,3.3
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SWB0,CONN16,CH3,PVDD3_3V_SYNTH_LDO_A5,3.3
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SWB0,CONN16,CH4,PVDD3_3V_SYNTH_LDO_B4,3.3
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SWB0,CONN16,CH5,PVDD3_3V_SYNTH_LDO_A4,3.3
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SWB0,CONN16,CH6,P3V3,3.3
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SWB0,CONN16,CH7,PVDD0_8V_T3,0.8
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SWB0,CONN16,CH1,P1V8_4,1.816
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SWB0,CONN16,CH2,PVDD3_3V_SYNTH_LDO_B5,3.38
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SWB0,CONN16,CH3,PVDD3_3V_SYNTH_LDO_A5,3.38
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SWB0,CONN16,CH4,PVDD3_3V_SYNTH_LDO_B4,3.38
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SWB0,CONN16,CH5,PVDD3_3V_SYNTH_LDO_A4,3.38
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SWB0,CONN16,CH6,P3V3,3.327
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SWB0,CONN16,CH7,PVDD0_8V_T3,0.82
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SWB0,CONN16,CH8,P0V75_DVDD_1,0.75
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SWB0,CONN16,CH9,P0V75_AVDD_1,0.75
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SWB0,CONN16,CH10,P1V5_AVDD_1,1.5
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SWB0,CONN16,CH11,P0V9_AVDD_1,0.9
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SWB0,CONN16,CH12,PVDD0V9_0,0.9
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SWB0,CONN16,CH13,PVDD0V9_1,0.9
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SWB0,CONN16,CH14,PVDD0V9_3,0.9
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SWB0,CONN16,CH15,PVDD1V2_T3,1.2
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SWB0,CONN16,CH9,P0V75_AVDD_1,0.756
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SWB0,CONN16,CH10,P1V5_AVDD_1,1.524
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SWB0,CONN16,CH11,P0V9_AVDD_1,0.915
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SWB0,CONN16,CH12,PVDD0V9_0,0.915
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SWB0,CONN16,CH13,PVDD0V9_1,0.91
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SWB0,CONN16,CH14,PVDD0V9_3,0.915
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SWB0,CONN16,CH15,PVDD1V2_T3,1.224
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SWB1,CONN13,CH0,P0V75_DVDD_47,0.75
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SWB1,CONN13,CH1,P0V75_AVDD_47,0.75
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SWB1,CONN13,CH2,P1V5_AVDD_47,1.5
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SWB1,CONN13,CH3,P0V9_AVDD_47,0.9
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SWB1,CONN13,CH4,P1V8_1,1.8
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SWB1,CONN13,CH5,PVDD3_3V_SYNTH_LDO_A3,3.3
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SWB1,CONN13,CH6,PVDD3_3V_SYNTH_LDO_B1,3.3
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SWB1,CONN13,CH7,P1V8_3,1.8
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SWB1,CONN13,CH1,P0V75_AVDD_47,0.756
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SWB1,CONN13,CH2,P1V5_AVDD_47,1.524
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SWB1,CONN13,CH3,P0V9_AVDD_47,0.915
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SWB1,CONN13,CH4,P1V8_1,1.816
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SWB1,CONN13,CH5,PVDD3_3V_SYNTH_LDO_A3,3.38
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SWB1,CONN13,CH6,PVDD3_3V_SYNTH_LDO_B1,3.38
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SWB1,CONN13,CH7,P1V8_3,1.816
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SWB1,CONN13,CH8,P1V8_DVDDIO_3,1.8
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SWB1,CONN13,CH9,P0V75_DVDD_39,0.75
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SWB1,CONN13,CH10,P0V75_AVDD_39,0.75
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SWB1,CONN13,CH11,P1V5_AVDD_39,1.5
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SWB1,CONN13,CH12,P0V9_AVDD_39,0.9
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SWB1,CONN13,CH10,P0V75_AVDD_39,0.756
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SWB1,CONN13,CH11,P1V5_AVDD_39,1.524
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SWB1,CONN13,CH12,P0V9_AVDD_39,0.915
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SWB1,CONN13,CH13,PVDD1V5_2,1.5
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SWB1,CONN13,CH14,PVDD1V8_DUT,1.8
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SWB1,CONN13,CH15,PVDD_MDIO,1.2
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SWB1,CONN14,CH0,P0V75_AVDD_7,0.75
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SWB1,CONN14,CH1,P1V5_AVDD_7,1.5
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SWB1,CONN14,CH2,P0V9_AVDD_7,0.9
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SWB1,CONN14,CH3,P1V8_5,1.8
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SWB1,CONN14,CH4,P1V8_2,1.8
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SWB1,CONN14,CH5,PVDD3_3V_SYNTH_LDO_B2,3.3
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SWB1,CONN14,CH6,PVDD3_3V_SYNTH_LDO_A2,3.3
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SWB1,CONN14,CH7,PVDD3_3V_SYNTH_LDO_A1,3.3
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SWB1,CONN14,CH8,PVDD1V5_TSC,1.5
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SWB1,CONN14,CH9,PVDD1V5_ANLG,1.5
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SWB1,CONN14,CH0,P0V75_AVDD_7,0.756
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SWB1,CONN14,CH1,P1V5_AVDD_7,1.524
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SWB1,CONN14,CH2,P0V9_AVDD_7,0.915
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SWB1,CONN14,CH3,P1V8_5,1.816
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SWB1,CONN14,CH4,P1V8_2,1.816
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SWB1,CONN14,CH5,PVDD3_3V_SYNTH_LDO_B2,3.38
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SWB1,CONN14,CH6,PVDD3_3V_SYNTH_LDO_A2,3.38
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SWB1,CONN14,CH7,PVDD3_3V_SYNTH_LDO_A1,3.38
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SWB1,CONN14,CH8,PVDD1V5_TSC,1.516
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SWB1,CONN14,CH9,PVDD1V5_ANLG,1.516
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SWB1,CONN14,CH10,NC,-
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SWB1,CONN14,CH11,NC,-
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SWB1,CONN14,CH12,PVDD1V5_1,1.5
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SWB1,CONN14,CH13,NC,-
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SWB1,CONN14,CH14,P1V8_DVDDIO_1,1.8
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SWB1,CONN14,CH15,P0V75_DVDD_7,0.75
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SWB1,CONN15,CH0,P1V5_AVDD_55,1.5
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SWB1,CONN15,CH1,P0V9_AVDD_55,0.9
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SWB1,CONN15,CH0,P1V5_AVDD_55,1.524
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SWB1,CONN15,CH1,P0V9_AVDD_55,0.915
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SWB1,CONN15,CH2,P0V75_DVDD_63,0.75
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SWB1,CONN15,CH3,P0V75_AVDD_63,0.75
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SWB1,CONN15,CH4,P1V5_AVDD_63,1.5
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SWB1,CONN15,CH5,P0V9_AVDD_63,0.9
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SWB1,CONN15,CH6,PVDD3_3V_SYNTH_LDO_B3,3.3
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SWB1,CONN15,CH3,P0V75_AVDD_63,0.756
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SWB1,CONN15,CH4,P1V5_AVDD_63,1.524
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SWB1,CONN15,CH5,P0V9_AVDD_63,0.915
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SWB1,CONN15,CH6,PVDD3_3V_SYNTH_LDO_B3,3.38
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SWB1,CONN15,CH7,PVDD1V5_3,1.5
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SWB1,CONN15,CH8,P0V85_STBY,0.85
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SWB1,CONN15,CH9,P1V8_STBY,1.8
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SWB1,CONN15,CH10,NC,-
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SWB1,CONN15,CH11,P3V3_STBY,3.3
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SWB1,CONN15,CH12,PVDD0V9_2,0.9
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SWB1,CONN15,CH12,PVDD0V9_2,0.91
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SWB1,CONN15,CH13,P0V75_DVDD_55,0.75
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SWB1,CONN15,CH14,P0V75_AVDD_55,0.75
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SWB1,CONN15,CH14,P0V75_AVDD_55,0.756
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SWB1,CONN15,CH15,P1V8_DVDDIO_4,1.8
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SWB1,CONN16,CH0,PVDD1V5_0,1.5
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SWB1,CONN16,CH1,P1V8_4,1.8
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SWB1,CONN16,CH2,PVDD3_3V_SYNTH_LDO_B5,3.3
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SWB1,CONN16,CH3,PVDD3_3V_SYNTH_LDO_A5,3.3
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SWB1,CONN16,CH4,PVDD3_3V_SYNTH_LDO_B4,3.3
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SWB1,CONN16,CH5,PVDD3_3V_SYNTH_LDO_A4,3.3
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SWB1,CONN16,CH6,P3V3,3.3
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SWB1,CONN16,CH7,PVDD0_8V_T3,0.8
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SWB1,CONN16,CH1,P1V8_4,1.816
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SWB1,CONN16,CH2,PVDD3_3V_SYNTH_LDO_B5,3.38
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SWB1,CONN16,CH3,PVDD3_3V_SYNTH_LDO_A5,3.38
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SWB1,CONN16,CH4,PVDD3_3V_SYNTH_LDO_B4,3.38
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SWB1,CONN16,CH5,PVDD3_3V_SYNTH_LDO_A4,3.38
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SWB1,CONN16,CH6,P3V3,3.327
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SWB1,CONN16,CH7,PVDD0_8V_T3,0.82
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SWB1,CONN16,CH8,P0V75_DVDD_1,0.75
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SWB1,CONN16,CH9,P0V75_AVDD_1,0.75
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SWB1,CONN16,CH10,P1V5_AVDD_1,1.5
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SWB1,CONN16,CH11,P0V9_AVDD_1,0.9
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SWB1,CONN16,CH12,PVDD0V9_0,0.9
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SWB1,CONN16,CH13,PVDD0V9_1,0.9
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SWB1,CONN16,CH14,PVDD0V9_3,0.9
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SWB1,CONN16,CH15,PVDD1V2_T3,1.2
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SWB1,CONN16,CH9,P0V75_AVDD_1,0.756
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SWB1,CONN16,CH10,P1V5_AVDD_1,1.524
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SWB1,CONN16,CH11,P0V9_AVDD_1,0.915
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SWB1,CONN16,CH12,PVDD0V9_0,0.915
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SWB1,CONN16,CH13,PVDD0V9_1,0.91
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SWB1,CONN16,CH14,PVDD0V9_3,0.915
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SWB1,CONN16,CH15,PVDD1V2_T3,1.224
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@@ -0,0 +1,59 @@
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# v1.1.3 — Margin now measures against what this platform actually runs at
|
||||
|
||||
## ✨ New features
|
||||
|
||||
**Per-CONN margin profiles for the switch boards**
|
||||
* `combo_SWB_CONN13_high` / `_low` through `combo_SWB_CONN16_high` / `_low` replace the old `comboA` / `comboB` pair. Each file's per-channel percentages follow the rails on *that* board, so a CONN13 profile is no longer a rough fit for CONN16.
|
||||
* SWB0 and SWB1 share a profile per CONN — the two boards carry identical rails and differ only by I2C bus.
|
||||
* A high pass and a low pass are now the same run with `_high` swapped for `_low`.
|
||||
* **A profile applied to the wrong CONN margins the wrong rails and says nothing.** The percentages are positional, so nothing detects the mismatch. `margin_apply_profile_all.sh` now names the right profile per board instead of one name for all nine.
|
||||
|
||||
## 🐛 Bug fixes
|
||||
|
||||
**`VNOM` was the spec value, not what the rails actually sit at**
|
||||
* 86 of the 144 channels moved up between +0.8% and +2.5% to the measured median for this platform — `PVDD3_3V_SYNTH_LDO_*` 3.3 → 3.38, `P0V9_AVDD_*` 0.9 → 0.915, `PVDD0_8V_T3` 0.8 → 0.82, and so on.
|
||||
* **This is not a display change.** `VNOM` is the denominator of `margin_status`'s deviation %, *and* the basis `margin_set` derives high / low / OV / UV from. A rail sitting steady at 0.756 V used to read `+0.80%` against a nominal 0.75 and now reads `0.00%`; and asking for `+3%` now lands on a different absolute voltage than it did last week.
|
||||
* **Margin logs from before and after this build cannot be compared directly.** The numbers moved because the reference moved, not because the hardware did.
|
||||
|
||||
**The batch profile script pointed at files that no longer exist**
|
||||
* `margin_apply_profile_all.sh` still named `comboA` for all nine boards. With `comboA.conf` removed, every board would have stopped at `Profile not found` — a nine-line wall of errors on a script that is normally left to run.
|
||||
|
||||
**The channel map CSV was stale**
|
||||
* `docs/LTC2980_channel_map.csv` is generated from `settings/*.conf`, so all 86 changed rails were wrong in it. Regenerated with `tools/gen_channel_map.sh`. It is output, not source — regenerate it, never hand-edit it.
|
||||
|
||||
## 📦 Downloads
|
||||
|
||||
| File | Contents |
|
||||
|---|---|
|
||||
| `Script_ABC_Blanton_V1.1.3.zip` | The full Tera Term working directory, including `Blanton_Script/` to copy onto the DUT |
|
||||
|
||||
**After copying to the DUT:**
|
||||
|
||||
```bash
|
||||
chmod +x ~/Blanton_Script/*.sh # see below
|
||||
grep -rlU $'\r' ~/Blanton_Script # expect no output
|
||||
```
|
||||
|
||||
`blanton_ber.sh` and `nfc_polling.sh` are invoked by the macros through `./` or `~/`, so they need the execute bit along with `bmc_monitor.sh` and `usb_target.sh` — neither git nor a Windows/USB copy carries it reliably.
|
||||
|
||||
## ⚠️ Before you run
|
||||
|
||||
* **Re-baseline your margin expectations.** Any pass/fail limits or golden logs derived from the old `VNOM` values need redoing against this build.
|
||||
* **`margin_save` in any form writes NVM permanently** and now writes margin windows derived from the new reference. Run `margin_status_all.sh` first and never call it during a test.
|
||||
* **SWB profiles are per-CONN.** Applying `combo_SWB_CONN13_high` to a CONN16 board is silently wrong.
|
||||
* **These three tests cannot share the switch**: `blanton_ber.sh`, `blanton_tr518.sh` and `blanton_traffic_linespeed`.
|
||||
* **PRBS takes the links down** while `blanton_ber.sh` is armed.
|
||||
* **`ce0` keeps running until you stop it.**
|
||||
* **Two numbers must stay in step**: Script C's `sleep 30` and `blanton_ber.sh`'s `BER_INTERVAL`.
|
||||
* **`FAN_SPEED` is 100** — the fans run flat out unless you change `config.ttl`.
|
||||
* **`nfc_polling.sh start` clears the log**, so Script B wipes Script A's NFC baseline file (the numbers are already in the console log).
|
||||
* **The NFC tool is written for the customer's tag.** It polls Type A / B / F only and parses Type A strictly; a tag of another technology is never discovered and fails as `no RF interface activation notification received`. Without `--expected-id` it does not check identity, so a different tag of the same type still passes.
|
||||
* **The three items listed as unverified in v1.1.0 are still unverified**: the `ce0` ingress mirror, the 120s settle in `blanton_tr518.sh`, and `test mode nr=no` on stop.
|
||||
|
||||
## 🔗 Links
|
||||
|
||||
* [ARCHITECTURE.md](https://etgit.et-wen.com/etwen/Blanton_TTL_Script/src/branch/main/ARCHITECTURE.md) — test flow, data models, constraints
|
||||
* [CLAUDE.md](https://etgit.et-wen.com/etwen/Blanton_TTL_Script/src/branch/main/CLAUDE.md) — commands and the bench gotchas
|
||||
* [LTC2980_channel_map.csv](https://etgit.et-wen.com/etwen/Blanton_TTL_Script/src/branch/main/docs/LTC2980_channel_map.csv) — all 144 margin channels with the new `VNOM`
|
||||
|
||||
**Full changelog:** [V1.1.2...V1.1.3](https://etgit.et-wen.com/etwen/Blanton_TTL_Script/compare/V1.1.2...V1.1.3)
|
||||
Reference in New Issue
Block a user