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feat(multiphase): Add a way back from a margin without a power cycle

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blanton_multiphase_margin.sh gains 'normal', which returns all 38 rails
to their nominal set point from tools/Multiphase_Normal.txt. Same rails,
same per-rail reporting, same -u 0|1|all as the margin profiles.

Until now the tool could apply high3/low3/comboA/comboB and commit with
save, but had no way to undo. That left a power cycle as the only exit -
and worse, a save run while still margined would have written the offsets
into NVM, which a power cycle does not undo either.

Emitted commands were diffed against the source file: argv identical.

The nominal labels in the source carry extra text ("0.900V (nominal)",
"0.8V(nominal) , 0.8591V with load line"); the per-rail line prints just
the voltage so the column matches the other profiles. The load-line note
is kept as a comment above the data block, because reading 0.859 V back
from TH6_CORE after 'normal' looks like a failed write and is not one.

Script A -> V1.1.7.

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_014RetWKFZFG1ZHcitQAyhwM
This commit is contained in:
etwen
2026-09-04 09:23:25 +08:00
co-authored by Claude Opus 5
parent 78a8f641c9
commit a9c56ee1d4
3 changed files with 405 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/Script_ABC_Blanton/1_Blanton_Script_A.ttl
+14 -2
View File
@@ -1,7 +1,7 @@
; =============================================================================
; Script A for Blanton
; Version : V1.1.6
; Date : 2026-09-02
; Version : V1.1.7
; Date : 2026-09-04
; Author : ETWen
; =============================================================================
; Version History:
@@ -277,6 +277,18 @@
; high and low while its neighbours sit the other way
; NC channels stay nominal in both (CONN14 CH10/11/13,
; CONN15 CH10) - nothing to margin on an unused rail
; V1.1.7 2026-09-04 Blanton_Script/blanton_multiphase_margin.sh v1.1.0 Add the 'normal' sub-command
; Puts all 38 rails back to their nominal set point,
; from tools/Multiphase_Normal.txt - same rails and the
; same per-rail reporting as the margin profiles
; Until now the only way back from a margin was a power
; cycle, and 'save' run while margined would have
; committed the offsets to NVM, where a power cycle does
; not help either
; !! TH6_CORE is 0.8 V nominal but settles near 0.8591 V
; once the load line is active - reading back 0.859
; after 'normal' is the load line, not a failed write
; tools/Multiphase_Normal.txt Bench command reference for the above
; =============================================================================
include "config.ttl"
src/Script_ABC_Blanton/Blanton_Script/blanton_multiphase_margin.sh
+203
View File
@@ -3,6 +3,12 @@
# blanton_multiphase_margin.sh -- multiphase VRM margin over the native i2c bus
# =============================================================================
# Version History:
# V1.1.0 2026-09-04 Add 'normal' - puts every rail back to its nominal set
# point, from tools/Multiphase_Normal.txt. Same 38 rails
# and the same per-rail reporting as the margin profiles.
# Without it the only way back from a margin was a power
# cycle, and 'save' would have committed the margined
# values to NVM where a power cycle does not help either.
# V1.0.0 2026-09-01 First version. Bash port of tools/Multiphase_*.txt.
# high3 / low3 / comboA / comboB / save, -u 0|1|all.
# =============================================================================
@@ -31,6 +37,7 @@
# ./blanton_multiphase_margin.sh low3 # all rails -3%
# ./blanton_multiphase_margin.sh comboA # mixed high/low, set A
# ./blanton_multiphase_margin.sh comboB # mixed high/low, set B
# ./blanton_multiphase_margin.sh normal # back to the nominal set point
# ./blanton_multiphase_margin.sh save # commit to NVM (permanent)
# ./blanton_multiphase_margin.sh high3 -u 0 # SWB0 only
# ./blanton_multiphase_margin.sh high3 -n # print commands, touch nothing
@@ -811,6 +818,200 @@ i2cset -f -y 14 0x20 0x00 0
i2ctransfer -f -y 14 w3@0x20 0x21 0x2D 0x01
"
# --- normal ---------------------------------------------------------------
# Back to the nominal set point. TH6_CORE is 0.8 V nominal but settles near
# 0.8591 V once the load line is active, so a margin_status style read after
# this will not show exactly 0.8 V on that rail - that is the load line, not
# a failed write.
MP_DATA_normal="\
@ SWB0_0V9_ANLG0 0.900V
i2cset -f -y 13 0x25 0x00 0
i2ctransfer -f -y 13 w3@0x25 0x21 0x83 0x00
i2cset -f -y 13 0x25 0x00 2
i2ctransfer -f -y 13 w3@0x25 0x0D 0x74 0x10
@ SWB0_0V9_ANLG1 0.900V
i2cset -f -y 15 0x26 0x00 0
i2ctransfer -f -y 15 w3@0x26 0x21 0x83 0x00
i2cset -f -y 15 0x26 0x00 2
i2ctransfer -f -y 15 w3@0x26 0x0D 0x74 0x10
@ SWB0_0V75_ANLG0 0.75V
i2cset -f -y 13 0x25 0x00 1
i2ctransfer -f -y 13 w3@0x25 0x21 0x65 0x00
i2cset -f -y 13 0x25 0x00 2
i2ctransfer -f -y 13 w3@0x25 0x1D 0x5A 0x06
@ SWB0_0V75_ANLG1 0.75V
i2cset -f -y 15 0x26 0x00 1
i2ctransfer -f -y 15 w3@0x26 0x21 0x65 0x00
i2cset -f -y 15 0x26 0x00 2
i2ctransfer -f -y 15 w3@0x26 0x1D 0x5A 0x06
@ SWB0_PHYTILE_P0 0.75V
i2cset -f -y 13 0x21 0x00 0
i2ctransfer -f -y 13 w3@0x21 0x21 0x65 0x00
i2cset -f -y 13 0x21 0x00 2
i2ctransfer -f -y 13 w3@0x21 0x0D 0xB2 0x0C
@ SWB0_PHYTILE_P1 0.75V
i2cset -f -y 13 0x21 0x00 1
i2ctransfer -f -y 13 w3@0x21 0x21 0x65 0x00
i2cset -f -y 13 0x21 0x00 2
i2ctransfer -f -y 13 w3@0x21 0x1D 0x5A 0x06
@ SWB0_PHYTILE_P2 0.75V
i2cset -f -y 13 0x22 0x00 0
i2ctransfer -f -y 13 w3@0x22 0x21 0x65 0x00
i2cset -f -y 13 0x22 0x00 2
i2ctransfer -f -y 13 w3@0x22 0x0D 0xB2 0x0C
@ SWB0_PHYTILE_P3 0.75V
i2cset -f -y 13 0x22 0x00 1
i2ctransfer -f -y 13 w3@0x22 0x21 0x65 0x00
i2cset -f -y 13 0x22 0x00 2
i2ctransfer -f -y 13 w3@0x22 0x1D 0x5A 0x06
@ SWB0_PHYTILE_P4 0.75V
i2cset -f -y 15 0x23 0x00 0
i2ctransfer -f -y 15 w3@0x23 0x21 0x65 0x00
i2cset -f -y 15 0x23 0x00 2
i2ctransfer -f -y 15 w3@0x23 0x0D 0xB2 0x0C
@ SWB0_PHYTILE_P5 0.75V
i2cset -f -y 15 0x23 0x00 1
i2ctransfer -f -y 15 w3@0x23 0x21 0x65 0x00
i2cset -f -y 15 0x23 0x00 2
i2ctransfer -f -y 15 w3@0x23 0x1D 0x5A 0x06
@ SWB0_PHYTILE_P6 0.75V
i2cset -f -y 15 0x24 0x00 0
i2ctransfer -f -y 15 w3@0x24 0x21 0x65 0x00
i2cset -f -y 15 0x24 0x00 2
i2ctransfer -f -y 15 w3@0x24 0x0D 0xB2 0x0C
@ SWB0_PHYTILE_P7 0.75V
i2cset -f -y 15 0x24 0x00 1
i2ctransfer -f -y 15 w3@0x24 0x21 0x65 0x00
i2cset -f -y 15 0x24 0x00 2
i2ctransfer -f -y 15 w3@0x24 0x1D 0x5A 0x06
@ SWB0_PVDD1V5_CNDR0 1.5V
i2cset -f -y 13 0x29 0x00 0
i2ctransfer -f -y 13 w3@0x29 0x21 0xFB 0x00
i2cset -f -y 13 0x29 0x00 2
i2ctransfer -f -y 13 w3@0x29 0x0D 0x71 0x1F
@ SWB0_PVDD1V5_CNDR1 1.5V
i2cset -f -y 13 0x29 0x00 1
i2ctransfer -f -y 13 w3@0x29 0x21 0xFB 0x00
i2cset -f -y 13 0x29 0x00 2
i2ctransfer -f -y 13 w3@0x29 0x1D 0xB9 0x0F
@ SWB0_PVDDA_PHYT0 0.720V
i2cset -f -y 13 0x27 0x00 0
i2ctransfer -f -y 13 w3@0x27 0x21 0x5F 0x00
i2cset -f -y 13 0x27 0x00 2
i2ctransfer -f -y 13 w3@0x27 0x0D 0xF4 0x0B
@ SWB0_PVDDA_PHYT1 0.720V
i2cset -f -y 13 0x27 0x00 1
i2ctransfer -f -y 13 w3@0x27 0x21 0x5F 0x00
i2cset -f -y 13 0x27 0x00 2
i2ctransfer -f -y 13 w3@0x27 0x1D 0xFC 0x05
@ SWB0_PVDDA_PHYT2 0.720V
i2cset -f -y 15 0x28 0x00 0
i2ctransfer -f -y 15 w3@0x28 0x21 0x5F 0x00
i2cset -f -y 15 0x28 0x00 2
i2ctransfer -f -y 15 w3@0x28 0x0D 0xF4 0x0B
@ SWB0_PVDDA_PHYT3 0.720V
i2cset -f -y 15 0x28 0x00 1
i2ctransfer -f -y 15 w3@0x28 0x21 0x5F 0x00
i2cset -f -y 15 0x28 0x00 2
i2ctransfer -f -y 15 w3@0x28 0x1D 0xFC 0x05
@ SWB0_TH6_CORE 0.8V
i2cset -f -y 13 0x20 0x00 0
i2ctransfer -f -y 13 w3@0x20 0x21 0x57 0x01
@ SWB1_0V9_ANLG0 0.900V
i2cset -f -y 14 0x25 0x00 0
i2ctransfer -f -y 14 w3@0x25 0x21 0x83 0x00
i2cset -f -y 14 0x25 0x00 2
i2ctransfer -f -y 14 w3@0x25 0x0D 0x74 0x10
@ SWB1_0V9_ANLG1 0.900V
i2cset -f -y 16 0x26 0x00 0
i2ctransfer -f -y 16 w3@0x26 0x21 0x83 0x00
i2cset -f -y 16 0x26 0x00 2
i2ctransfer -f -y 16 w3@0x26 0x0D 0x74 0x10
@ SWB1_0V75_ANLG0 0.75V
i2cset -f -y 14 0x25 0x00 1
i2ctransfer -f -y 14 w3@0x25 0x21 0x65 0x00
i2cset -f -y 14 0x25 0x00 2
i2ctransfer -f -y 14 w3@0x25 0x1D 0x5A 0x06
@ SWB1_0V75_ANLG1 0.75V
i2cset -f -y 16 0x26 0x00 1
i2ctransfer -f -y 16 w3@0x26 0x21 0x65 0x00
i2cset -f -y 16 0x26 0x00 2
i2ctransfer -f -y 16 w3@0x26 0x1D 0x5A 0x06
@ SWB1_PHYTILE_P0 0.75V
i2cset -f -y 14 0x21 0x00 0
i2ctransfer -f -y 14 w3@0x21 0x21 0x65 0x00
i2cset -f -y 14 0x21 0x00 2
i2ctransfer -f -y 14 w3@0x21 0x0D 0xB2 0x0C
@ SWB1_PHYTILE_P1 0.75V
i2cset -f -y 14 0x21 0x00 1
i2ctransfer -f -y 14 w3@0x21 0x21 0x65 0x00
i2cset -f -y 14 0x21 0x00 2
i2ctransfer -f -y 14 w3@0x21 0x1D 0x5A 0x06
@ SWB1_PHYTILE_P2 0.75V
i2cset -f -y 14 0x22 0x00 0
i2ctransfer -f -y 14 w3@0x22 0x21 0x65 0x00
i2cset -f -y 14 0x22 0x00 2
i2ctransfer -f -y 14 w3@0x22 0x0D 0xB2 0x0C
@ SWB1_PHYTILE_P3 0.75V
i2cset -f -y 14 0x22 0x00 1
i2ctransfer -f -y 14 w3@0x22 0x21 0x65 0x00
i2cset -f -y 14 0x22 0x00 2
i2ctransfer -f -y 14 w3@0x22 0x1D 0x5A 0x06
@ SWB1_PHYTILE_P4 0.75V
i2cset -f -y 16 0x23 0x00 0
i2ctransfer -f -y 16 w3@0x23 0x21 0x65 0x00
i2cset -f -y 16 0x23 0x00 2
i2ctransfer -f -y 16 w3@0x23 0x0D 0xB2 0x0C
@ SWB1_PHYTILE_P5 0.75V
i2cset -f -y 16 0x23 0x00 1
i2ctransfer -f -y 16 w3@0x23 0x21 0x65 0x00
i2cset -f -y 16 0x23 0x00 2
i2ctransfer -f -y 16 w3@0x23 0x1D 0x5A 0x06
@ SWB1_PHYTILE_P6 0.75V
i2cset -f -y 16 0x24 0x00 0
i2ctransfer -f -y 16 w3@0x24 0x21 0x65 0x00
i2cset -f -y 16 0x24 0x00 2
i2ctransfer -f -y 16 w3@0x24 0x0D 0xB2 0x0C
@ SWB1_PHYTILE_P7 0.75V
i2cset -f -y 16 0x24 0x00 1
i2ctransfer -f -y 16 w3@0x24 0x21 0x65 0x00
i2cset -f -y 16 0x24 0x00 2
i2ctransfer -f -y 16 w3@0x24 0x1D 0x5A 0x06
@ SWB1_PVDD1V5_CNDR0 1.5V
i2cset -f -y 14 0x29 0x00 0
i2ctransfer -f -y 14 w3@0x29 0x21 0xFB 0x00
i2cset -f -y 14 0x29 0x00 2
i2ctransfer -f -y 14 w3@0x29 0x0D 0x71 0x1F
@ SWB1_PVDD1V5_CNDR1 1.5V
i2cset -f -y 14 0x29 0x00 1
i2ctransfer -f -y 14 w3@0x29 0x21 0xFB 0x00
i2cset -f -y 14 0x29 0x00 2
i2ctransfer -f -y 14 w3@0x29 0x1D 0xB9 0x0F
@ SWB1_PVDDA_PHYT0 0.720V
i2cset -f -y 14 0x27 0x00 0
i2ctransfer -f -y 14 w3@0x27 0x21 0x5F 0x00
i2cset -f -y 14 0x27 0x00 2
i2ctransfer -f -y 14 w3@0x27 0x0D 0xF4 0x0B
@ SWB1_PVDDA_PHYT1 0.720V
i2cset -f -y 14 0x27 0x00 1
i2ctransfer -f -y 14 w3@0x27 0x21 0x5F 0x00
i2cset -f -y 14 0x27 0x00 2
i2ctransfer -f -y 14 w3@0x27 0x1D 0xFC 0x05
@ SWB1_PVDDA_PHYT2 0.720V
i2cset -f -y 16 0x28 0x00 0
i2ctransfer -f -y 16 w3@0x28 0x21 0x5F 0x00
i2cset -f -y 16 0x28 0x00 2
i2ctransfer -f -y 16 w3@0x28 0x0D 0xF4 0x0B
@ SWB1_PVDDA_PHYT3 0.720V
i2cset -f -y 16 0x28 0x00 1
i2ctransfer -f -y 16 w3@0x28 0x21 0x5F 0x00
i2cset -f -y 16 0x28 0x00 2
i2ctransfer -f -y 16 w3@0x28 0x1D 0xFC 0x05
@ SWB1_TH6_CORE 0.8V
i2cset -f -y 14 0x20 0x00 0
i2ctransfer -f -y 14 w3@0x20 0x21 0x57 0x01
"
# --- save: STORE_USER_ALL per controller, no per-rail mapping ---------------
MP_DATA_save="\
i2cset -f -y 13 0x25 0x00 0
@@ -1007,6 +1208,7 @@ blanton_multiphase_margin.sh - multiphase VRM margin (native i2c, 38 rails)
low3 every rail -3%
comboA mixed high/low, set A
comboB mixed high/low, set B
normal back to the nominal set point (undo a margin without a power cycle)
save commit to NVM -- PERMANENT, survives a power cycle
-u|--unit <0|1|all> SWB0 (i2c-13/15) / SWB1 (i2c-14/16); default both
@@ -1041,6 +1243,7 @@ case "${SUB}" in
low3) _mp_apply low3 "${MP_DATA_low3}" ;;
comboA) _mp_apply comboA "${MP_DATA_comboA}" ;;
comboB) _mp_apply comboB "${MP_DATA_comboB}" ;;
normal) _mp_apply normal "${MP_DATA_normal}" ;;
save) _mp_save ;;
-h|--help|"") usage ;;
*) _mp_err "unknown sub-command: ${SUB}"; usage; exit 1 ;;