From ababb2c3d12ea5fe3d9b90a0cb5ca0aaef920739 Mon Sep 17 00:00:00 2001 From: ETWen Date: Wed, 19 Aug 2026 12:10:39 +0800 Subject: [PATCH] fix(margin): Correct SWB I2C channels and LTC2977 addresses from bench Verified against the DUT. Two things were wrong in the SWB confs. Channel assignment: CONN13/CONN15 and CONN14/CONN16 were paired the wrong way round. The bench wiring is SWB0 Ch6 = CONN14/CONN16 Ch8 = CONN13/CONN15 SWB1 Ch7 = CONN14/CONN16 Ch9 = CONN13/CONN15 LTC2977 addresses: the high half of each LTC2980 was recorded one step above the low half (0x5C/0x5D, 0x62/0x63). These are 7-bit addresses derived from 8-bit pairs, so they step by two: 0x5C/0x5E and 0x62/0x64. This also clears the collision noted in v2.6.0, where SWB0_CONN13 chip2 and SWB0_CONN14 chip1 both landed on 0x5E on Ch6. Each channel now carries two disjoint address pairs (0x5C/0x5E and 0x62/0x64), verified collision-free across all eight SWB confs. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_014RetWKFZFG1ZHcitQAyhwM --- .../LTC2980_Margin_Script/settings/Blanton_SWB0_CONN13.conf | 2 +- .../LTC2980_Margin_Script/settings/Blanton_SWB0_CONN14.conf | 4 ++-- .../LTC2980_Margin_Script/settings/Blanton_SWB0_CONN15.conf | 2 +- .../LTC2980_Margin_Script/settings/Blanton_SWB0_CONN16.conf | 6 +++--- .../LTC2980_Margin_Script/settings/Blanton_SWB1_CONN13.conf | 4 ++-- .../LTC2980_Margin_Script/settings/Blanton_SWB1_CONN14.conf | 4 ++-- .../LTC2980_Margin_Script/settings/Blanton_SWB1_CONN15.conf | 2 +- .../LTC2980_Margin_Script/settings/Blanton_SWB1_CONN16.conf | 6 +++--- 8 files changed, 15 insertions(+), 15 deletions(-) diff --git a/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN13.conf b/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN13.conf index 0e4b344..1e72880 100644 --- a/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN13.conf +++ b/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN13.conf @@ -9,7 +9,7 @@ # --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach # it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. --- TRANSPORT="swb" -CB_I2C_CH=6 # CB F3 Ch6 = SWB0 CONN13/CONN14 (shared with CONN14, addr must differ) +CB_I2C_CH=8 # CB F3 Ch6 = SWB0 CONN13/CONN14 (shared with CONN14, addr must differ) # --- I2C Configuration --- diff --git a/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN14.conf b/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN14.conf index 39f95e2..f49e4d9 100644 --- a/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN14.conf +++ b/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN14.conf @@ -16,8 +16,8 @@ CB_I2C_CH=6 # CB F3 Ch6 = SWB0 CONN13/CONN14 (shared with CONN13, addr # Format: "bus:address" (8 channels per entry / per LTC2977) CHIPS=( # chip1: SWB0 (CONN14) - "0:0x5E" # CH0 ~ CH7 - "0:0x5F" # CH8 ~ CH15 + "0:0x5C" # CH0 ~ CH7 + "0:0x5E" # CH8 ~ CH15 ) # Pre-commands to run before accessing each chip (empty = none) diff --git a/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN15.conf b/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN15.conf index dc018fe..3ee2d9a 100644 --- a/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN15.conf +++ b/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN15.conf @@ -17,7 +17,7 @@ CB_I2C_CH=8 # CB F3 Ch8 = SWB0 CONN15/CONN16 (shared with CONN16, addr CHIPS=( # chip1: SWB0 (CONN15) "0:0x62" # CH0 ~ CH7 - "0:0x63" # CH8 ~ CH15 + "0:0x64" # CH8 ~ CH15 ) # Pre-commands to run before accessing each chip (empty = none) diff --git a/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN16.conf b/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN16.conf index 3a05621..f34637b 100644 --- a/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN16.conf +++ b/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN16.conf @@ -9,15 +9,15 @@ # --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach # it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. --- TRANSPORT="swb" -CB_I2C_CH=8 # CB F3 Ch8 = SWB0 CONN15/CONN16 (shared with CONN15, addr must differ) +CB_I2C_CH=6 # CB F3 Ch8 = SWB0 CONN15/CONN16 (shared with CONN15, addr must differ) # --- I2C Configuration --- # Format: "bus:address" (8 channels per entry / per LTC2977) CHIPS=( # chip1: SWB0 (CONN16) - "0:0x64" # CH0 ~ CH7 - "0:0x65" # CH8 ~ CH15 + "0:0x62" # CH0 ~ CH7 + "0:0x64" # CH8 ~ CH15 ) # Pre-commands to run before accessing each chip (empty = none) diff --git a/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN13.conf b/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN13.conf index 742e38f..a42fe68 100644 --- a/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN13.conf +++ b/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN13.conf @@ -9,7 +9,7 @@ # --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach # it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. --- TRANSPORT="swb" -CB_I2C_CH=7 # CB F3 Ch7 = SWB1 CONN13/CONN14 (shared with CONN14, addr must differ) +CB_I2C_CH=9 # CB F3 Ch7 = SWB1 CONN13/CONN14 (shared with CONN14, addr must differ) # --- I2C Configuration --- @@ -17,7 +17,7 @@ CB_I2C_CH=7 # CB F3 Ch7 = SWB1 CONN13/CONN14 (shared with CONN14, addr CHIPS=( # chip1: SWB1 (CONN13) "1:0x5C" # CH0 ~ CH7 - "1:0x5D" # CH8 ~ CH15 + "1:0x5E" # CH8 ~ CH15 ) # Pre-commands to run before accessing each chip (empty = none) diff --git a/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN14.conf b/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN14.conf index e2efc1a..62891d8 100644 --- a/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN14.conf +++ b/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN14.conf @@ -16,8 +16,8 @@ CB_I2C_CH=7 # CB F3 Ch7 = SWB1 CONN13/CONN14 (shared with CONN13, addr # Format: "bus:address" (8 channels per entry / per LTC2977) CHIPS=( # chip1: SWB1 (CONN14) - "1:0x5E" # CH0 ~ CH7 - "1:0x5F" # CH8 ~ CH15 + "1:0x5C" # CH0 ~ CH7 + "1:0x5E" # CH8 ~ CH15 ) # Pre-commands to run before accessing each chip (empty = none) diff --git a/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN15.conf b/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN15.conf index d341e4a..12d5e87 100644 --- a/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN15.conf +++ b/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN15.conf @@ -17,7 +17,7 @@ CB_I2C_CH=9 # CB F3 Ch9 = SWB1 CONN15/CONN16 (shared with CONN16, addr CHIPS=( # chip1: SWB1 (CONN15) "1:0x62" # CH0 ~ CH7 - "1:0x63" # CH8 ~ CH15 + "1:0x64" # CH8 ~ CH15 ) # Pre-commands to run before accessing each chip (empty = none) diff --git a/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN16.conf b/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN16.conf index 5f4bd2a..f0d3d0c 100644 --- a/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN16.conf +++ b/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN16.conf @@ -9,15 +9,15 @@ # --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach # it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. --- TRANSPORT="swb" -CB_I2C_CH=9 # CB F3 Ch9 = SWB1 CONN15/CONN16 (shared with CONN15, addr must differ) +CB_I2C_CH=7 # CB F3 Ch9 = SWB1 CONN15/CONN16 (shared with CONN15, addr must differ) # --- I2C Configuration --- # Format: "bus:address" (8 channels per entry / per LTC2977) CHIPS=( # chip1: SWB1 (CONN16) - "1:0x64" # CH0 ~ CH7 - "1:0x65" # CH8 ~ CH15 + "1:0x62" # CH0 ~ CH7 + "1:0x64" # CH8 ~ CH15 ) # Pre-commands to run before accessing each chip (empty = none)