diff --git a/.gitattributes b/.gitattributes
new file mode 100644
index 0000000..c80f391
--- /dev/null
+++ b/.gitattributes
@@ -0,0 +1,29 @@
+# =============================================================================
+# 換行符政策
+# -----------------------------------------------------------------------------
+# 這個 repo 同時被 Windows（Tera Term 端編輯）與 SONiC/Linux（DUT 端執行）使用，
+# 所以必須明確指定，不能靠各機器的 core.autocrlf。
+#
+# 踩過的坑：margin.sh 帶著 CRLF 進 repo，scp 到 DUT 後 bash 直接掛：
+#     -bash: $'\r': command not found
+#     syntax error near unexpected token `$'{\r''
+# settings/*.conf 同樣危險 —— margin_init 是用 source 讀它們的，未加引號的
+# 賦值（例如 CB_I2C_CH=6）會變成 "6\r"，SWB transport 會拿著壞掉的通道號去打 I2C。
+# =============================================================================
+
+# 在 DUT / Linux 上執行或被 source 的，一律 LF
+*.sh    text eol=lf
+*.conf  text eol=lf
+*.py    text eol=lf
+*.txt   text eol=lf
+*.md    text eol=lf
+
+# Tera Term macro 只在 Windows 上跑，維持 CRLF；標成 -text 讓 git 原樣保存，
+# 避免對既有檔案產生大量純換行符的假 diff
+*.ttl   -text
+
+# 二進位，不要做任何轉換
+*.xlsx  binary
+*.docx  binary
+*.pdf   binary
+*.h5    binary
diff --git a/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/margin.sh b/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/margin.sh
index cad6f97..1ade2f6 100644
--- a/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/margin.sh
+++ b/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/margin.sh
@@ -1,754 +1,754 @@
-#!/bin/bash
-# Blanton Margin Tool - Shell version (CB: i2cset/i2cget | SWB: cb_pmbus_* via FPGA)
-# Usage: source margin.sh; margin_init; margin_status
-#
-# =============================================================================
-# Version Control
-# -----------------------------------------------------------------------------
-# v2.6.0  SWB path actually wired to the shared CB I2C package. blanton_cb_i2c.sh
-#         and blanton_fpga_pcimem.sh live in the PARENT dir (Blanton_Script/), not
-#         next to margin.sh, so the backend is now searched in both places.
-#         Adds, for TRANSPORT=swb only (CB/i2c path untouched):
-#           * cb_i2c_init <ch> once in margin_init (prescale 0x88 = 100kHz) and
-#             CB_I2C_AUTO_INIT=0 afterwards -> 4 fewer pcimem writes per transfer
-#           * cb_pmbus_read presence probe of every LTC2977 in CHIPS
-#           * return-code checking on every cb_pmbus_read/write (NACK is reported
-#             instead of silently reading 0x0000)
-#           * DEBUG_MODE collision fix: blanton_fpga_pcimem.sh uses the same var
-#             name, so pcimem tracing is gated by MARGIN_SWB_PCIMEM_DEBUG
-#           * margin_swb_* wrappers (info/probe/scan/reset/sem) for debugging
-#         Physical map: CB F3 Ch6=SWB0 CONN13/14, Ch8=SWB0 CONN15/16,
-#                       Ch7=SWB1 CONN13/14, Ch9=SWB1 CONN15/16
-# v2.5.0  SWB margin support via a per-conf TRANSPORT layer. The SWB margin
-#         boards are ALSO LTC2980 (2x LTC2977) -- same chip as CB -- just reached
-#         through the CB FPGA F3 I2C master instead of a native bus. So the whole
-#         stack above the wire (PAGE, LINEAR16 x8192, VNOM margin) is identical;
-#         only the wire op changes. A .conf sets:
-#            TRANSPORT="swb"   CB_I2C_CH=<6|7|8|9>
-#         and i2cset/i2cget are swapped for cb_pmbus_write/cb_pmbus_read (from the
-#         bundled blanton_cb_i2c.sh + blanton_fpga_pcimem.sh) on that FPGA channel.
-#         The LTC2977 addresses stay in CHIPS; the bus field is unused for swb.
-#         TRANSPORT unset -> "i2c", so existing CB confs are unchanged.
-# v2.4.0  Auto-enable channel before margining: clear ON_OFF_CONFIG use_control
-#         (0x02=0x1a) so OPERATION can turn the channel on and soft-connect the
-#         servo DAC. Fixes "STATUS_WORD OFF=1, Vout won't move" on rails the
-#         LTC2980 does not sequence (externally enabled, e.g. MPQ8625 always-on).
-#         margin_set does NOT block for servo settle — confirm final voltages
-#         with margin_status afterwards. RAM-only; reverts on power cycle.
-# v2.3.1  Fix: LINEAR16 hex->dec parsing (SONiC busybox/mawk ignores "0x")
-# v2.3.0  Logging system, TAB completion, colored output
-# v2.2.0  margin_debug toggle + colored log output
-# v2.1.0  Batch scripts for status / apply_profile / save across boards
-# v2.0.0  Per-LTC2980 .conf, Script Channel mapping, scoped PRE/POST (breaking)
-# v1.2.0  Per-chip PRE/POST command hooks
-# v1.1.0  Replace i2cexec with i2cset/i2cget, rename to LTC2980
-# v1.0.0  Initial release - LTC2977 PMBus margin test tool
-# =============================================================================
-
-SCRIPT_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
-SETTINGS_DIR="$SCRIPT_DIR/settings"
-PROFILES_DIR="$SCRIPT_DIR/profiles"
-LOGS_DIR="$SCRIPT_DIR/logs"
-
-# --- Ensure logs directory exists ---
-mkdir -p "$LOGS_DIR"
-
-# --- Global state ---
-PART_NUMBER=""
-CHIPS=()
-DEBUG_MODE=0
-LOG_MODE=1
-
-# Transport backend, selected per-conf (a .conf sets TRANSPORT):
-#   "i2c" (default) - LTC2980 on the CPU I2C bus via i2cset/i2cget
-#   "swb"           - the SAME LTC2980 margin board, but reached through the CB
-#                     FPGA F3 I2C master via cb_pmbus_read/cb_pmbus_write. The
-#                     LTC2977 addresses stay in CHIPS; CB_I2C_CH picks the FPGA
-#                     I2C channel (6/7/8/9). Everything above the wire (PAGE,
-#                     LINEAR16 x8192, VNOM margin) is identical to the i2c path.
-TRANSPORT="i2c"
-CB_I2C_CH=""
-
-# --- SWB transport backend (blanton_cb_i2c.sh + blanton_fpga_pcimem.sh) -------
-# The SWB margin boards' LTC2980s hang off the CB FPGA Function 3 I2C master.
-# Physical mapping (per bench wiring):
-#   CB F3 Ch6 -> SWB0 CONN13 / CONN14
-#   CB F3 Ch8 -> SWB0 CONN15 / CONN16
-#   CB F3 Ch7 -> SWB1 CONN13 / CONN14
-#   CB F3 Ch9 -> SWB1 CONN15 / CONN16
-# Two CONNs share one FPGA I2C channel, so the two boards on a channel MUST use
-# different LTC2977 slave addresses (the CHIPS array in each .conf).
-MARGIN_SWB_CHANNELS="${MARGIN_SWB_CHANNELS:-6 7 8 9}"
-# SCL prescale for cb_i2c_init: 0x88 = 100kHz, 0x24 = 400kHz (@75MHz core clk).
-MARGIN_SWB_PRESCALE_LO="${MARGIN_SWB_PRESCALE_LO:-0x88}"
-MARGIN_SWB_PRESCALE_HI="${MARGIN_SWB_PRESCALE_HI:-0x00}"
-# 0 = cb_i2c_init once in margin_init, then CB_I2C_AUTO_INIT=0 so each
-# cb_pmbus_* transfer skips the 4-register prescale/enable dance (much faster:
-# margin_status all = 32 transfers). Set 1 to keep the package default (re-init
-# on every transfer) if something else on the box reprograms the channel.
-MARGIN_SWB_AUTO_INIT="${MARGIN_SWB_AUTO_INIT:-0}"
-# 1 = grab the per-channel FPGA semaphore (cb_i2c_sem acquire) in margin_init and
-# hold it for the whole session; margin_swb_sem_release frees it. Default off so
-# margin never fails just because someone else holds it.
-MARGIN_SWB_USE_SEM="${MARGIN_SWB_USE_SEM:-0}"
-# 1 = probe every LTC2977 in CHIPS (PMBus PAGE read) at margin_init.
-MARGIN_SWB_PROBE="${MARGIN_SWB_PROBE:-1}"
-# 1 = also let blanton_fpga_pcimem.sh print every underlying pcimem command.
-# Needed because that script's debug flag is ALSO called DEBUG_MODE; margin_debug
-# would otherwise flood the console with pcimem lines.
-MARGIN_SWB_PCIMEM_DEBUG="${MARGIN_SWB_PCIMEM_DEBUG:-0}"
-_SWB_READY=0
-_SWB_SEM_HELD=0
-
-# Channel enable for margining. Rails the LTC2980 does not sequence (externally
-# enabled, e.g. an always-on MPQ8625 buck) sit with STATUS_WORD OFF=1 and won't
-# margin, because the servo DAC never soft-connects. Writing ON_OFF_CONFIG (0x02)
-# to clear use_control lets a following OPERATION command turn the channel on so
-# the DAC connects and servos to the margin target. Change is RAM-only and reverts
-# on power cycle (never STORE_USER_ALL during a test). Set MARGIN_AUTO_ENABLE=0 to
-# keep the stored ON_OFF_CONFIG untouched.
-MARGIN_AUTO_ENABLE=1
-ONOFF_ENABLE_VALUE="0x1a"   # controlled_on=1, use_pmbus=1, use_control=0, b1=1
-# Short pause after OPERATION so the write registers; NOT a full servo settle.
-# margin_set returns immediately (does not block per channel) — the DAC soft-connect
-# + servo ramp takes a few seconds, so confirm final voltages yourself with
-# margin_status after all channels are set. Bump this if you want margin_set's own
-# read-back to reflect the settled value.
-MARGIN_SETTLE="0.3"
-_BUS=""
-_ADDR=""
-_PRE_SCOPE=""   # set while inside a PRE/POST wrapped operation; prevents nested re-entry
-_LOG_FILE=""
-_LOG_DETAIL_FILE=""
-_LOG_DETAIL_LINE=0
-
-# --- Logging helper ---
-_ts() {
-    date "+%Y-%m-%d %H:%M:%S.%3N"
-}
-
-_log() {
-    [ "$LOG_MODE" = "0" ] && return
-    [ -z "$_LOG_FILE" ] && return
-    echo -e "[$(_ts)] $*" >> "$_LOG_FILE"
-}
-
-_log_detail() {
-    [ "$LOG_MODE" = "0" ] && return
-    [ -z "$_LOG_DETAIL_FILE" ] && return
-    (( _LOG_DETAIL_LINE++ ))
-    echo "[$(_ts)] $*" >> "$_LOG_DETAIL_FILE"
-}
-
-_log_label() {
-    [ "$LOG_MODE" = "0" ] && return
-    local label=$1
-    (( _LOG_DETAIL_LINE++ ))
-    echo "[$(_ts)] --- $label ---" >> "$_LOG_DETAIL_FILE"
-    _log "$label \033[90m(detail Line:${_LOG_DETAIL_LINE})\033[0m"
-}
-
-_log_start_session() {
-    _log "--- margin_init: $PART_NUMBER ---"
-}
-
-# --- Toggle log mode ---
-margin_log() {
-    if [ "${1:-}" = "on" ]; then
-        LOG_MODE=1
-    elif [ "${1:-}" = "off" ]; then
-        LOG_MODE=0
-    else
-        [ "$LOG_MODE" = "0" ] && LOG_MODE=1 || LOG_MODE=0
-    fi
-    echo -e "[\033[34mINFO\033[0m] LOG_MODE=$LOG_MODE"
-}
-
-# --- Toggle debug mode ---
-margin_debug() {
-    if [ "${1:-}" = "on" ]; then
-        DEBUG_MODE=1
-    elif [ "${1:-}" = "off" ]; then
-        DEBUG_MODE=0
-    else
-        [ "$DEBUG_MODE" = "0" ] && DEBUG_MODE=1 || DEBUG_MODE=0
-    fi
-    echo -e "[\033[34mINFO\033[0m] DEBUG_MODE=$DEBUG_MODE"
-}
-
-# =============================================================================
-# SWB transport backend (TRANSPORT=swb only -- the CB/i2c path never gets here)
-# -----------------------------------------------------------------------------
-# Wire ops come from the shared CB I2C package:
-#   blanton_fpga_pcimem.sh -> cb_fpga <fn> <off> [data]   (PCIe BAR via pcimem)
-#   blanton_cb_i2c.sh      -> cb_i2c_init / cb_i2c_reset / cb_i2c_sem /
-#                             cb_i2c_scan / cb_pmbus_read / cb_pmbus_write
-# Both live in the parent Blanton_Script/ directory (a copy next to margin.sh is
-# also honoured if you ever bundle one).
-# =============================================================================
-
-# Locate a backend script: next to margin.sh first, then the parent dir.
-_swb_find_backend() {
-    local name="$1" p
-    for p in "$SCRIPT_DIR/$name" "$SCRIPT_DIR/../$name"; do
-        [ -f "$p" ] && { echo "$p"; return 0; }
-    done
-    return 1
-}
-
-# Source blanton_fpga_pcimem.sh (cb_fpga) + blanton_cb_i2c.sh (cb_pmbus_*).
-_swb_backend_load() {
-    local f
-    if ! declare -F cb_fpga >/dev/null 2>&1; then
-        if f=$(_swb_find_backend "blanton_fpga_pcimem.sh"); then
-            # shellcheck source=/dev/null
-            source "$f"
-            echo -e "[\033[34mINFO\033[0m] SWB backend: sourced $f"
-        else
-            echo -e "[\033[31mERRO\033[0m] blanton_fpga_pcimem.sh not found in $SCRIPT_DIR or its parent"
-            return 1
-        fi
-    fi
-    if ! declare -F cb_pmbus_read >/dev/null 2>&1; then
-        if f=$(_swb_find_backend "blanton_cb_i2c.sh"); then
-            # shellcheck source=/dev/null
-            source "$f" >/dev/null
-            echo -e "[\033[34mINFO\033[0m] SWB backend: sourced $f"
-        else
-            echo -e "[\033[31mERRO\033[0m] blanton_cb_i2c.sh not found in $SCRIPT_DIR or its parent"
-            return 1
-        fi
-    fi
-    declare -F cb_pmbus_read >/dev/null 2>&1 || {
-        echo -e "[\033[31mERRO\033[0m] cb_pmbus_read still undefined after sourcing the backend"; return 1; }
-    return 0
-}
-
-# Run a cb_* command with pcimem tracing suppressed (shared DEBUG_MODE var).
-# Echoes the command's stdout, preserves its return code.
-_swb_call() {
-    local _saved="$DEBUG_MODE" _rc
-    [ "$MARGIN_SWB_PCIMEM_DEBUG" = "1" ] || DEBUG_MODE=0
-    "$@"
-    _rc=$?
-    DEBUG_MODE="$_saved"
-    return $_rc
-}
-
-# Probe one LTC2977: 1-byte PMBus read of PAGE (0x00). Returns cb_pmbus_read's rc.
-_swb_probe_addr() {
-    _swb_call cb_pmbus_read "$CB_I2C_CH" "$1" 0x00 1 >/dev/null 2>&1
-}
-
-# --- SWB wire ops used by the transport switch below ------------------------
-# Both use _ADDR (LTC2977 7-bit slave) set by _get_chip and CB_I2C_CH from the
-# .conf. Unlike i2cset/i2cget these report failures: a NACK on the FPGA I2C
-# master used to silently turn into Vout=0.0000.
-
-# _swb_write <reg> <byte> [byte...]   -> cb_pmbus_write (LSB first for LINEAR16)
-_swb_write() {
-    local reg=$1; shift
-    [ "$DEBUG_MODE" = "1" ] && echo -e "\033[90m[DEBG] cb_pmbus_write $CB_I2C_CH $_ADDR $reg $*\033[0m"
-    if ! _swb_call cb_pmbus_write "$CB_I2C_CH" "$_ADDR" "$reg" "$@" >/dev/null 2>&1; then
-        echo -e "[\033[31mERRO\033[0m] cb_pmbus_write ch=$CB_I2C_CH $_ADDR reg=$reg failed (NACK/timeout)" >&2
-        _log_detail "ERRO cb_pmbus_write ch=$CB_I2C_CH $_ADDR $reg $*"
-        return 1
-    fi
-    return 0
-}
-
-# _swb_read_word <reg>  -> echoes "0xXXXX" parsed out of cb_pmbus_read's "=> 0xXXXX"
-_swb_read_word() {
-    local reg=$1 out word
-    [ "$DEBUG_MODE" = "1" ] && echo -e "\033[90m[DEBG] cb_pmbus_read $CB_I2C_CH $_ADDR $reg 2\033[0m" >&2
-    if ! out=$(_swb_call cb_pmbus_read "$CB_I2C_CH" "$_ADDR" "$reg" 2 2>/dev/null); then
-        echo -e "[\033[31mERRO\033[0m] cb_pmbus_read ch=$CB_I2C_CH $_ADDR reg=$reg failed (NACK/timeout)" >&2
-        _log_detail "ERRO cb_pmbus_read ch=$CB_I2C_CH $_ADDR $reg"
-        echo "0x0000"
-        return 1
-    fi
-    # cb_pmbus_read prints "  [PMB-R] ... => 0xXXXX  raw=[...] linear16=..."
-    word=$(printf '%s' "$out" | awk -F'=> ' 'NF>1{print $2}' | awk '{print $1}')
-    [[ "$word" =~ ^0[xX][0-9a-fA-F]+$ ]] || word="0x0000"
-    echo "$word"
-}
-
-# Bring up the FPGA I2C channel for this .conf: validate CB_I2C_CH, prescale +
-# enable it once (cb_i2c_init), optionally take the semaphore, then probe CHIPS.
-_swb_setup() {
-    _SWB_READY=0
-
-    if [ -z "$CB_I2C_CH" ]; then
-        echo -e "[\033[31mERRO\033[0m] TRANSPORT=swb but CB_I2C_CH is empty in the .conf"
-        return 1
-    fi
-    if ! [[ "$CB_I2C_CH" =~ ^[0-9]+$ ]] || [ "$CB_I2C_CH" -gt 17 ]; then
-        echo -e "[\033[31mERRO\033[0m] CB_I2C_CH='$CB_I2C_CH' invalid (CB F3 I2C channels are 0..17)"
-        return 1
-    fi
-    case " $MARGIN_SWB_CHANNELS " in
-        *" $CB_I2C_CH "*) ;;
-        *) echo -e "[\033[33mWARN\033[0m] CB_I2C_CH=$CB_I2C_CH is not a known SWB VRM channel ($MARGIN_SWB_CHANNELS)" ;;
-    esac
-
-    # Prescale + MOD_EN on this channel.
-    if ! _swb_call cb_i2c_init "$CB_I2C_CH" "$MARGIN_SWB_PRESCALE_LO" "$MARGIN_SWB_PRESCALE_HI"; then
-        echo -e "[\033[31mERRO\033[0m] cb_i2c_init $CB_I2C_CH failed (FPGA/pcimem access?)"
-        return 1
-    fi
-    CB_I2C_AUTO_INIT="$MARGIN_SWB_AUTO_INIT"
-    local _khz="?"; [ "$MARGIN_SWB_PRESCALE_LO" = "0x88" ] && _khz="100"
-    [ "$MARGIN_SWB_PRESCALE_LO" = "0x24" ] && _khz="400"
-    echo -e "[\033[34mINFO\033[0m] cb_i2c_init ch=$CB_I2C_CH prescale=$MARGIN_SWB_PRESCALE_LO/$MARGIN_SWB_PRESCALE_HI (~${_khz}kHz), CB_I2C_AUTO_INIT=$CB_I2C_AUTO_INIT"
-    _log "swb: cb_i2c_init ch=$CB_I2C_CH prescale=$MARGIN_SWB_PRESCALE_LO auto_init=$CB_I2C_AUTO_INIT"
-
-    if [ "$MARGIN_SWB_USE_SEM" = "1" ]; then
-        if _swb_call cb_i2c_sem "$CB_I2C_CH" acquire; then
-            _SWB_SEM_HELD=1
-        else
-            echo -e "[\033[33mWARN\033[0m] semaphore on ch=$CB_I2C_CH not acquired; continuing without it"
-        fi
-    fi
-
-    _SWB_READY=1
-
-    if [ "$MARGIN_SWB_PROBE" = "1" ]; then
-        local idx=0 chip addr bad=0
-        for chip in "${CHIPS[@]}"; do
-            IFS=':' read -r _ addr <<< "$chip"
-            if _swb_probe_addr "$addr"; then
-                echo -e "[\033[34mINFO\033[0m] probe ch=$CB_I2C_CH LTC2977[$idx] $addr : \033[32mACK\033[0m"
-            else
-                echo -e "[\033[33mWARN\033[0m] probe ch=$CB_I2C_CH LTC2977[$idx] $addr : \033[31mNACK\033[0m (wrong CB_I2C_CH / addr, board absent, or channel stuck -> margin_swb_scan / margin_swb_reset)"
-                bad=1
-            fi
-            idx=$((idx+1))
-        done
-        _log "swb: probe ch=$CB_I2C_CH chips=${CHIPS[*]} $( [ "$bad" = "0" ] && echo all-ACK || echo has-NACK )"
-    fi
-    return 0
-}
-
-# --- SWB debug / maintenance wrappers (thin shells over blanton_cb_i2c.sh) ---
-_swb_guard() {
-    if [ "$TRANSPORT" != "swb" ]; then
-        echo -e "[\033[33mWARN\033[0m] current setting is TRANSPORT=$TRANSPORT (not swb); nothing to do"
-        return 1
-    fi
-    declare -F cb_pmbus_read >/dev/null 2>&1 || { echo -e "[\033[31mERRO\033[0m] SWB backend not loaded; run margin_init first"; return 1; }
-    return 0
-}
-
-# margin_swb_info -- show the transport wiring of the loaded setting
-margin_swb_info() {
-    echo "-------------"
-    echo "[$PART_NUMBER] transport"
-    echo "-------------"
-    echo "  TRANSPORT   : $TRANSPORT"
-    if [ "$TRANSPORT" = "swb" ]; then
-        echo "  CB_I2C_CH   : $CB_I2C_CH  (CB FPGA F3, base $(printf '0x%X' $(( 0x300 + CB_I2C_CH * 0x20 ))))"
-        echo "  LTC2977     : ${CHIPS[*]}  (bus field unused on swb)"
-        echo "  prescale    : $MARGIN_SWB_PRESCALE_LO/$MARGIN_SWB_PRESCALE_HI   auto_init=$CB_I2C_AUTO_INIT   sem_held=$_SWB_SEM_HELD"
-        echo "  wire ops    : cb_pmbus_write $CB_I2C_CH <addr> 0x00 <page> / cb_pmbus_read $CB_I2C_CH <addr> 0x8b 2"
-    else
-        echo "  bus:addr    : ${CHIPS[*]}  (i2cset/i2cget)"
-    fi
-}
-
-# margin_swb_probe -- re-run the PAGE-read presence check on every LTC2977
-margin_swb_probe() {
-    _swb_guard || return 1
-    local idx=0 chip addr
-    for chip in "${CHIPS[@]}"; do
-        IFS=':' read -r _ addr <<< "$chip"
-        if _swb_probe_addr "$addr"; then
-            echo -e "  ch=$CB_I2C_CH $addr : \033[32mACK\033[0m"
-        else
-            echo -e "  ch=$CB_I2C_CH $addr : \033[31mNACK\033[0m"
-        fi
-        idx=$((idx+1))
-    done
-}
-
-# margin_swb_scan [ch] -- cb_i2c_scan on this conf's channel (0x08..0x77)
-margin_swb_scan() {
-    _swb_guard || return 1
-    _swb_call cb_i2c_scan "${1:-$CB_I2C_CH}"
-}
-
-# margin_swb_reset -- local I2C controller reset (0xD) + re-init, for a stuck bus
-margin_swb_reset() {
-    _swb_guard || return 1
-    _swb_call cb_i2c_reset "$CB_I2C_CH"
-    _swb_call cb_i2c_init "$CB_I2C_CH" "$MARGIN_SWB_PRESCALE_LO" "$MARGIN_SWB_PRESCALE_HI"
-    echo -e "[\033[34mINFO\033[0m] ch=$CB_I2C_CH reset + re-init done"
-    _log "swb: cb_i2c_reset + cb_i2c_init ch=$CB_I2C_CH"
-}
-
-# margin_swb_sem [status|acquire|release]
-margin_swb_sem() {
-    _swb_guard || return 1
-    local act="${1:-status}"
-    _swb_call cb_i2c_sem "$CB_I2C_CH" "$act"
-    case "$act" in
-        acquire) _SWB_SEM_HELD=1 ;;
-        release) _SWB_SEM_HELD=0 ;;
-    esac
-}
-
-# margin_swb_sem_release -- release the session semaphore if margin_init took it
-margin_swb_sem_release() {
-    [ "$_SWB_SEM_HELD" = "1" ] || { echo -e "[\033[34mINFO\033[0m] no semaphore held by this session"; return 0; }
-    _swb_call cb_i2c_sem "$CB_I2C_CH" release
-    _SWB_SEM_HELD=0
-}
-
-# --- Init: load setting by name ---
-margin_init() {
-    if [ -z "$1" ]; then
-        echo -e "[\033[31mERRO\033[0m] Usage: margin_init <PART_NUMBER>"
-        return 1
-    fi
-    PART_NUMBER="$1"
-    echo "Part Number: $PART_NUMBER"
-
-    local setting_file="$SETTINGS_DIR/${PART_NUMBER}.conf"
-    if [ ! -f "$setting_file" ]; then
-        echo -e "[\033[31mERRO\033[0m] Setting file not found: $setting_file"
-        return 1
-    fi
-    TRANSPORT="i2c"; CB_I2C_CH=""   # reset before sourcing; swb confs override
-    source "$setting_file"
-    TRANSPORT="${TRANSPORT:-i2c}"    # a blank TRANSPORT="" in a .conf means i2c
-    echo -e "[\033[34mINFO\033[0m] Loaded setting: $setting_file (transport=$TRANSPORT)"
-
-    # SWB rails need the cb_pmbus_* backend (blanton_cb_i2c.sh + blanton_fpga_pcimem.sh,
-    # normally in the parent Blanton_Script/ dir); load it and bring the FPGA I2C
-    # channel up once. CB/i2c settings skip this entirely.
-    _SWB_READY=0; _SWB_SEM_HELD=0
-    if [ "$TRANSPORT" = "swb" ]; then
-        _swb_backend_load || return 1
-        _swb_setup || return 1
-    fi
-    _log_start_session
-}
-
-# --- Tab completion for margin_init ---
-_margin_init_completions() {
-    [ "$COMP_CWORD" -ne 1 ] && return
-    local cur="${COMP_WORDS[COMP_CWORD]}"
-    local names=$(ls "$SETTINGS_DIR"/*.conf 2>/dev/null | xargs -n1 basename | sed 's/\.conf$//')
-    COMPREPLY=($(compgen -W "$names" -- "$cur"))
-}
-complete -F _margin_init_completions margin_init
-
-# --- PRE/POST scope helpers ---
-# PRE/POST run once at the outermost public-function entry/exit.
-# Nested calls (e.g. margin_apply_profile -> margin_set -> margin_read_vout)
-# see _PRE_SCOPE already set and skip, so the mux only switches once.
-_run_cmds() {
-    local cmds=$1 label=$2
-    [ -z "$cmds" ] && return
-    IFS=';' read -ra _cmds <<< "$cmds"
-    for _cmd in "${_cmds[@]}"; do
-        _cmd=$(echo "$_cmd" | xargs)
-        [ -z "$_cmd" ] && continue
-        [ "$DEBUG_MODE" = "1" ] && echo -e "\033[36m$label $_cmd\033[0m"
-        eval "$_cmd" >/dev/null 2>&1
-    done
-}
-
-# Returns 0 (true) if caller owns the scope and must call _pre_exit on the way out.
-_pre_enter_own() {
-    if [ -z "$_PRE_SCOPE" ]; then
-        _PRE_SCOPE=1
-        _run_cmds "${CHIP_PRE_CMD[0]}" "[PRE]"
-        return 0
-    fi
-    return 1
-}
-
-_pre_exit() {
-    _run_cmds "${CHIP_POST_CMD[0]}" "[POST]"
-    _PRE_SCOPE=""
-}
-
-# --- Helper: set _BUS and _ADDR from channel number ---
-# Both transports use CHIPS (LTC2977 addresses). For swb the bus field is unused
-# (the FPGA I2C channel comes from CB_I2C_CH); _ADDR is the PMBus slave.
-_get_chip() {
-    local chip_idx=$(( $1 / 8 ))
-    IFS=':' read -r _BUS _ADDR <<< "${CHIPS[$chip_idx]}"
-}
-
-# --- Helper: get page (channel within LTC2977, 0x00~0x07) ---
-_get_page() {
-    printf "0x%02x" $(( $1 % 8 ))
-}
-
-# --- I2C low-level helpers (use _BUS/_ADDR set by _get_chip) ---
-# TRANSPORT=swb swaps the i2cset/i2cget wire op for cb_pmbus_* on CB_I2C_CH.
-# PAGE is written the same way on both (PMBus command 0x00).
-_open_page() {
-    if [ "$TRANSPORT" = "swb" ]; then
-        _swb_write 0x00 "$1"
-        return
-    fi
-    [ "$DEBUG_MODE" = "1" ] && echo -e "\033[90m[DEBG] i2cset -y $_BUS $_ADDR 0x00 $1 b\033[0m"
-    i2cset -y "$_BUS" "$_ADDR" 0x00 "$1" b >/dev/null 2>&1
-}
-
-# Write a 16-bit word (LINEAR16, little-endian: lo byte first).
-_i2c_write_word() {
-    local reg=$1 lo=$2 hi=$3
-    if [ "$TRANSPORT" = "swb" ]; then
-        _swb_write "$reg" "$lo" "$hi"
-        return
-    fi
-    local word=$(( (hi << 8) | lo ))
-    local word_hex=$(printf "0x%04x" "$word")
-    [ "$DEBUG_MODE" = "1" ] && echo -e "\033[90m[DEBG] i2cset -y $_BUS $_ADDR $reg $word_hex w\033[0m"
-    i2cset -y "$_BUS" "$_ADDR" "$reg" "$word" w >/dev/null 2>&1
-}
-
-_i2c_write_byte() {
-    if [ "$TRANSPORT" = "swb" ]; then
-        _swb_write "$1" "$2"
-        return
-    fi
-    [ "$DEBUG_MODE" = "1" ] && echo -e "\033[90m[DEBG] i2cset -y $_BUS $_ADDR $1 $2 b\033[0m"
-    i2cset -y "$_BUS" "$_ADDR" "$1" "$2" b >/dev/null 2>&1
-}
-
-# Read a 16-bit word; echoes "0xXXXX". For swb, parse cb_pmbus_read's "=> 0xXXXX".
-_i2c_read_word() {
-    if [ "$TRANSPORT" = "swb" ]; then
-        _swb_read_word "$1"
-        return
-    fi
-    [ "$DEBUG_MODE" = "1" ] && echo -e "\033[90m[DEBG] i2cget -y $_BUS $_ADDR $1 w\033[0m" >&2
-    local result
-    result=$(i2cget -y "$_BUS" "$_ADDR" "$1" w 2>/dev/null)
-    if [ -z "$result" ]; then
-        echo "0x0000"
-    else
-        echo "$result"
-    fi
-}
-
-# --- Enable current channel for margining (clear ON_OFF_CONFIG use_control) ---
-# Assumes _get_chip + _open_page already ran (uses current _BUS/_ADDR/page).
-# Lets a subsequent OPERATION command turn the channel on so the servo DAC
-# soft-connects; without this, rails the LTC2980 doesn't sequence stay OFF and
-# margining has no effect. RAM-only; a power cycle restores the stored value.
-_enable_channel() {
-    _i2c_write_byte 0x02 "$ONOFF_ENABLE_VALUE"
-}
-
-# --- Helper: decimal to LINEAR16 (returns "lo hi" hex strings) ---
-_dec_to_lin16() {
-    local value=$1
-    if [ "$value" = "0" ]; then
-        echo "0x00 0x00"
-        return
-    fi
-    local raw=$(awk "BEGIN { printf \"%04X\", int($value * 8192) }")
-    local hi=${raw:0:2}
-    local lo=${raw:2:2}
-    echo "0x${lo} 0x${hi}"
-}
-
-# --- Helper: LINEAR16 word to decimal voltage ---
-# i2cget returns a hex string like "0x9fc2". SONiC's awk (busybox/mawk) does NOT
-# parse a "0x" prefix in arithmetic and treats it as 0, so convert hex -> decimal
-# with bash arithmetic $(( )) first, then feed the decimal to awk.
-_lin16_to_dec() {
-    local raw_word=$(( ${1:-0} ))
-    awk "BEGIN { printf \"%.4f\", $raw_word / 8192.0 }"
-}
-
-# --- Read Vout for a channel ---
-margin_read_vout() {
-    local ch=$1
-    local vnom_var="CH${ch}_VNOM"
-    local net_var="CH${ch}_NET"
-    local vnom=${!vnom_var}
-    local net=${!net_var}
-
-    if [ "$vnom" = "-" ] || [ -z "$vnom" ]; then
-        printf "CH %2d: Channel not used\n" "$ch"
-        LAST_VOUT="0"
-        return
-    fi
-
-    local _own=0
-    _pre_enter_own && _own=1
-
-    _get_chip "$ch"
-    _open_page "$(_get_page "$ch")"
-    local raw
-    raw=$(_i2c_read_word 0x8b)
-    local vout=$(_lin16_to_dec "$raw")
-
-    local pct
-    pct=$(awk "BEGIN { printf \"%+.3f\", ($vout - $vnom) / $vnom * 100 }")
-    local _line
-    printf -v _line "CH %2d: Vnom = %.3f, Vout = %s (%s%%). Net - %s" "$ch" "$vnom" "$vout" "$pct" "$net"
-    echo "$_line"
-    _log_detail "$_line"
-    LAST_VOUT="$vout"
-
-    [ "$_own" = "1" ] && _pre_exit
-}
-
-# --- Status: read all or specific channel ---
-margin_status() {
-    local ch_in=${1:-all}
-    echo "-------------"
-    echo "[$PART_NUMBER] Channel status"
-    echo "-------------"
-    _log_label "margin_status [$PART_NUMBER] ch=$ch_in"
-
-    local _own=0
-    _pre_enter_own && _own=1
-
-    if [ "$ch_in" = "all" ]; then
-        for i in $(seq 0 15); do
-            local vnom_var="CH${i}_VNOM"
-            [ -n "${!vnom_var}" ] && margin_read_vout "$i"
-        done
-    else
-        margin_read_vout "$ch_in"
-    fi
-
-    [ "$_own" = "1" ] && _pre_exit
-}
-
-# --- Set margin value (write high/low + OV/UV) ---
-margin_set_value() {
-    local ch=$1 vnom=$2 change=$3 ovuv=${4:-2}
-
-    local high_val low_val ov_val uv_val
-    high_val=$(_dec_to_lin16 "$(awk "BEGIN { print $vnom * (1 + $change/100) }")")
-    low_val=$(_dec_to_lin16 "$(awk "BEGIN { print $vnom * (1 - $change/100) }")")
-    ov_val=$(_dec_to_lin16 "$(awk "BEGIN { print $vnom * (1 + ($change+$ovuv)/100) }")")
-    uv_val=$(_dec_to_lin16 "$(awk "BEGIN { print $vnom * (1 - ($change+$ovuv)/100) }")")
-
-    local _own=0
-    _pre_enter_own && _own=1
-
-    _get_chip "$ch"
-    _open_page "$(_get_page "$ch")"
-
-    local hi lo
-    read lo hi <<< $high_val
-    _i2c_write_word 0x25 "$lo" "$hi"
-    read lo hi <<< $low_val
-    _i2c_write_word 0x26 "$lo" "$hi"
-    read lo hi <<< $ov_val
-    _i2c_write_word 0x40 "$lo" "$hi"
-    read lo hi <<< $uv_val
-    _i2c_write_word 0x44 "$lo" "$hi"
-
-    [ "$_own" = "1" ] && _pre_exit
-}
-
-# --- Set operation register ---
-margin_operation() {
-    local ch=$1 op=$2
-
-    local op_val
-    case "$op" in
-        high)    op_val=0xa8 ;;
-        low)     op_val=0x98 ;;
-        nominal) op_val=0x80 ;;
-        off)     op_val=0x00 ;;
-        *)       echo -e "[\033[31mERRO\033[0m] invalid operation '$op'"; return 1 ;;
-    esac
-
-    local _own=0
-    _pre_enter_own && _own=1
-
-    _get_chip "$ch"
-    _open_page "$(_get_page "$ch")"
-    # Let OPERATION turn the channel on (soft-connect DAC) even on rails the
-    # LTC2980 does not sequence; skip when turning the channel off.
-    [ "$MARGIN_AUTO_ENABLE" = "1" ] && [ "$op" != "off" ] && _enable_channel
-    _i2c_write_byte 0x01 "$op_val"
-    sleep "$MARGIN_SETTLE"
-
-    [ "$_own" = "1" ] && _pre_exit
-}
-
-# --- Set: combined set_value + operation + verify ---
-margin_set() {
-    local ch=$1 op=$2 change=$3
-    local vnom_var="CH${ch}_VNOM"
-    local vnom=${!vnom_var}
-
-    if [ "$vnom" = "-" ] || [ -z "$vnom" ]; then
-        printf "CH %2d: Channel not used\n" "$ch"
-        return
-    fi
-
-    local _own=0
-    _pre_enter_own && _own=1
-
-    margin_set_value "$ch" "$vnom" "$change"
-    margin_operation "$ch" "$op"
-    margin_read_vout "$ch"
-    local _line
-    printf -v _line "CH %2d: Set %s %s%% done (Vout=%s)" "$ch" "$op" "$change" "$LAST_VOUT"
-    echo "$_line"
-    _log_detail "$_line"
-    _log "$(printf 'margin_set CH%2d %-7s %3s%% Vout=%-8s' $ch $op $change $LAST_VOUT)\033[90m(detail Line:${_LOG_DETAIL_LINE})\033[0m"
-
-    [ "$_own" = "1" ] && _pre_exit
-}
-
-# --- Apply a margin profile file ---
-margin_apply_profile() {
-    local profile=${1:-"$PROFILES_DIR/${PART_NUMBER}_default.conf"}
-    if [ ! -f "$profile" ]; then
-        echo -e "[\033[31mERRO\033[0m] Profile not found: $profile"
-        return 1
-    fi
-    echo "Applying profile: $profile"
-    _log_label "margin_apply_profile [$PART_NUMBER] $profile"
-    source "$profile"
-
-    local _own=0
-    _pre_enter_own && _own=1
-
-    for entry in "${PROFILE_CHANNELS[@]}"; do
-        local ch op change
-        IFS=':' read -r ch op change <<< "$entry"
-        margin_set "$ch" "$op" "$change"
-    done
-
-    [ "$_own" = "1" ] && _pre_exit
-}
-
-# --- Save to NVM ---
-margin_save() {
-    local _own=0
-    _pre_enter_own && _own=1
-
-    for chip in "${CHIPS[@]}"; do
-        IFS=':' read -r _BUS _ADDR <<< "$chip"
-        _i2c_write_byte 0x15 0x00
-    done
-    echo "Change Saved (${#CHIPS[@]} chips)"
-    _log_label "margin_save $PART_NUMBER (${#CHIPS[@]} chips)"
-
-    [ "$_own" = "1" ] && _pre_exit
-}
-
-if [ -z "$_LOG_FILE" ]; then
-    _LOG_FILE="$LOGS_DIR/margin_$(date '+%Y%m%d_%H%M%S').log"
-    _LOG_DETAIL_FILE="${_LOG_FILE%.log}_detail.log"
-    _log "=== Session start ==="
-    _log "Detail log: $_LOG_DETAIL_FILE"
-fi
-
-echo -e "[\033[34mINFO\033[0m] LTC2980 Margin Tool loaded. Run 'margin_init' to start."
+#!/bin/bash
+# Blanton Margin Tool - Shell version (CB: i2cset/i2cget | SWB: cb_pmbus_* via FPGA)
+# Usage: source margin.sh; margin_init; margin_status
+#
+# =============================================================================
+# Version Control
+# -----------------------------------------------------------------------------
+# v2.6.0  SWB path actually wired to the shared CB I2C package. blanton_cb_i2c.sh
+#         and blanton_fpga_pcimem.sh live in the PARENT dir (Blanton_Script/), not
+#         next to margin.sh, so the backend is now searched in both places.
+#         Adds, for TRANSPORT=swb only (CB/i2c path untouched):
+#           * cb_i2c_init <ch> once in margin_init (prescale 0x88 = 100kHz) and
+#             CB_I2C_AUTO_INIT=0 afterwards -> 4 fewer pcimem writes per transfer
+#           * cb_pmbus_read presence probe of every LTC2977 in CHIPS
+#           * return-code checking on every cb_pmbus_read/write (NACK is reported
+#             instead of silently reading 0x0000)
+#           * DEBUG_MODE collision fix: blanton_fpga_pcimem.sh uses the same var
+#             name, so pcimem tracing is gated by MARGIN_SWB_PCIMEM_DEBUG
+#           * margin_swb_* wrappers (info/probe/scan/reset/sem) for debugging
+#         Physical map: CB F3 Ch6=SWB0 CONN13/14, Ch8=SWB0 CONN15/16,
+#                       Ch7=SWB1 CONN13/14, Ch9=SWB1 CONN15/16
+# v2.5.0  SWB margin support via a per-conf TRANSPORT layer. The SWB margin
+#         boards are ALSO LTC2980 (2x LTC2977) -- same chip as CB -- just reached
+#         through the CB FPGA F3 I2C master instead of a native bus. So the whole
+#         stack above the wire (PAGE, LINEAR16 x8192, VNOM margin) is identical;
+#         only the wire op changes. A .conf sets:
+#            TRANSPORT="swb"   CB_I2C_CH=<6|7|8|9>
+#         and i2cset/i2cget are swapped for cb_pmbus_write/cb_pmbus_read (from the
+#         bundled blanton_cb_i2c.sh + blanton_fpga_pcimem.sh) on that FPGA channel.
+#         The LTC2977 addresses stay in CHIPS; the bus field is unused for swb.
+#         TRANSPORT unset -> "i2c", so existing CB confs are unchanged.
+# v2.4.0  Auto-enable channel before margining: clear ON_OFF_CONFIG use_control
+#         (0x02=0x1a) so OPERATION can turn the channel on and soft-connect the
+#         servo DAC. Fixes "STATUS_WORD OFF=1, Vout won't move" on rails the
+#         LTC2980 does not sequence (externally enabled, e.g. MPQ8625 always-on).
+#         margin_set does NOT block for servo settle — confirm final voltages
+#         with margin_status afterwards. RAM-only; reverts on power cycle.
+# v2.3.1  Fix: LINEAR16 hex->dec parsing (SONiC busybox/mawk ignores "0x")
+# v2.3.0  Logging system, TAB completion, colored output
+# v2.2.0  margin_debug toggle + colored log output
+# v2.1.0  Batch scripts for status / apply_profile / save across boards
+# v2.0.0  Per-LTC2980 .conf, Script Channel mapping, scoped PRE/POST (breaking)
+# v1.2.0  Per-chip PRE/POST command hooks
+# v1.1.0  Replace i2cexec with i2cset/i2cget, rename to LTC2980
+# v1.0.0  Initial release - LTC2977 PMBus margin test tool
+# =============================================================================
+
+SCRIPT_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
+SETTINGS_DIR="$SCRIPT_DIR/settings"
+PROFILES_DIR="$SCRIPT_DIR/profiles"
+LOGS_DIR="$SCRIPT_DIR/logs"
+
+# --- Ensure logs directory exists ---
+mkdir -p "$LOGS_DIR"
+
+# --- Global state ---
+PART_NUMBER=""
+CHIPS=()
+DEBUG_MODE=0
+LOG_MODE=1
+
+# Transport backend, selected per-conf (a .conf sets TRANSPORT):
+#   "i2c" (default) - LTC2980 on the CPU I2C bus via i2cset/i2cget
+#   "swb"           - the SAME LTC2980 margin board, but reached through the CB
+#                     FPGA F3 I2C master via cb_pmbus_read/cb_pmbus_write. The
+#                     LTC2977 addresses stay in CHIPS; CB_I2C_CH picks the FPGA
+#                     I2C channel (6/7/8/9). Everything above the wire (PAGE,
+#                     LINEAR16 x8192, VNOM margin) is identical to the i2c path.
+TRANSPORT="i2c"
+CB_I2C_CH=""
+
+# --- SWB transport backend (blanton_cb_i2c.sh + blanton_fpga_pcimem.sh) -------
+# The SWB margin boards' LTC2980s hang off the CB FPGA Function 3 I2C master.
+# Physical mapping (per bench wiring):
+#   CB F3 Ch6 -> SWB0 CONN13 / CONN14
+#   CB F3 Ch8 -> SWB0 CONN15 / CONN16
+#   CB F3 Ch7 -> SWB1 CONN13 / CONN14
+#   CB F3 Ch9 -> SWB1 CONN15 / CONN16
+# Two CONNs share one FPGA I2C channel, so the two boards on a channel MUST use
+# different LTC2977 slave addresses (the CHIPS array in each .conf).
+MARGIN_SWB_CHANNELS="${MARGIN_SWB_CHANNELS:-6 7 8 9}"
+# SCL prescale for cb_i2c_init: 0x88 = 100kHz, 0x24 = 400kHz (@75MHz core clk).
+MARGIN_SWB_PRESCALE_LO="${MARGIN_SWB_PRESCALE_LO:-0x88}"
+MARGIN_SWB_PRESCALE_HI="${MARGIN_SWB_PRESCALE_HI:-0x00}"
+# 0 = cb_i2c_init once in margin_init, then CB_I2C_AUTO_INIT=0 so each
+# cb_pmbus_* transfer skips the 4-register prescale/enable dance (much faster:
+# margin_status all = 32 transfers). Set 1 to keep the package default (re-init
+# on every transfer) if something else on the box reprograms the channel.
+MARGIN_SWB_AUTO_INIT="${MARGIN_SWB_AUTO_INIT:-0}"
+# 1 = grab the per-channel FPGA semaphore (cb_i2c_sem acquire) in margin_init and
+# hold it for the whole session; margin_swb_sem_release frees it. Default off so
+# margin never fails just because someone else holds it.
+MARGIN_SWB_USE_SEM="${MARGIN_SWB_USE_SEM:-0}"
+# 1 = probe every LTC2977 in CHIPS (PMBus PAGE read) at margin_init.
+MARGIN_SWB_PROBE="${MARGIN_SWB_PROBE:-1}"
+# 1 = also let blanton_fpga_pcimem.sh print every underlying pcimem command.
+# Needed because that script's debug flag is ALSO called DEBUG_MODE; margin_debug
+# would otherwise flood the console with pcimem lines.
+MARGIN_SWB_PCIMEM_DEBUG="${MARGIN_SWB_PCIMEM_DEBUG:-0}"
+_SWB_READY=0
+_SWB_SEM_HELD=0
+
+# Channel enable for margining. Rails the LTC2980 does not sequence (externally
+# enabled, e.g. an always-on MPQ8625 buck) sit with STATUS_WORD OFF=1 and won't
+# margin, because the servo DAC never soft-connects. Writing ON_OFF_CONFIG (0x02)
+# to clear use_control lets a following OPERATION command turn the channel on so
+# the DAC connects and servos to the margin target. Change is RAM-only and reverts
+# on power cycle (never STORE_USER_ALL during a test). Set MARGIN_AUTO_ENABLE=0 to
+# keep the stored ON_OFF_CONFIG untouched.
+MARGIN_AUTO_ENABLE=1
+ONOFF_ENABLE_VALUE="0x1a"   # controlled_on=1, use_pmbus=1, use_control=0, b1=1
+# Short pause after OPERATION so the write registers; NOT a full servo settle.
+# margin_set returns immediately (does not block per channel) — the DAC soft-connect
+# + servo ramp takes a few seconds, so confirm final voltages yourself with
+# margin_status after all channels are set. Bump this if you want margin_set's own
+# read-back to reflect the settled value.
+MARGIN_SETTLE="0.3"
+_BUS=""
+_ADDR=""
+_PRE_SCOPE=""   # set while inside a PRE/POST wrapped operation; prevents nested re-entry
+_LOG_FILE=""
+_LOG_DETAIL_FILE=""
+_LOG_DETAIL_LINE=0
+
+# --- Logging helper ---
+_ts() {
+    date "+%Y-%m-%d %H:%M:%S.%3N"
+}
+
+_log() {
+    [ "$LOG_MODE" = "0" ] && return
+    [ -z "$_LOG_FILE" ] && return
+    echo -e "[$(_ts)] $*" >> "$_LOG_FILE"
+}
+
+_log_detail() {
+    [ "$LOG_MODE" = "0" ] && return
+    [ -z "$_LOG_DETAIL_FILE" ] && return
+    (( _LOG_DETAIL_LINE++ ))
+    echo "[$(_ts)] $*" >> "$_LOG_DETAIL_FILE"
+}
+
+_log_label() {
+    [ "$LOG_MODE" = "0" ] && return
+    local label=$1
+    (( _LOG_DETAIL_LINE++ ))
+    echo "[$(_ts)] --- $label ---" >> "$_LOG_DETAIL_FILE"
+    _log "$label \033[90m(detail Line:${_LOG_DETAIL_LINE})\033[0m"
+}
+
+_log_start_session() {
+    _log "--- margin_init: $PART_NUMBER ---"
+}
+
+# --- Toggle log mode ---
+margin_log() {
+    if [ "${1:-}" = "on" ]; then
+        LOG_MODE=1
+    elif [ "${1:-}" = "off" ]; then
+        LOG_MODE=0
+    else
+        [ "$LOG_MODE" = "0" ] && LOG_MODE=1 || LOG_MODE=0
+    fi
+    echo -e "[\033[34mINFO\033[0m] LOG_MODE=$LOG_MODE"
+}
+
+# --- Toggle debug mode ---
+margin_debug() {
+    if [ "${1:-}" = "on" ]; then
+        DEBUG_MODE=1
+    elif [ "${1:-}" = "off" ]; then
+        DEBUG_MODE=0
+    else
+        [ "$DEBUG_MODE" = "0" ] && DEBUG_MODE=1 || DEBUG_MODE=0
+    fi
+    echo -e "[\033[34mINFO\033[0m] DEBUG_MODE=$DEBUG_MODE"
+}
+
+# =============================================================================
+# SWB transport backend (TRANSPORT=swb only -- the CB/i2c path never gets here)
+# -----------------------------------------------------------------------------
+# Wire ops come from the shared CB I2C package:
+#   blanton_fpga_pcimem.sh -> cb_fpga <fn> <off> [data]   (PCIe BAR via pcimem)
+#   blanton_cb_i2c.sh      -> cb_i2c_init / cb_i2c_reset / cb_i2c_sem /
+#                             cb_i2c_scan / cb_pmbus_read / cb_pmbus_write
+# Both live in the parent Blanton_Script/ directory (a copy next to margin.sh is
+# also honoured if you ever bundle one).
+# =============================================================================
+
+# Locate a backend script: next to margin.sh first, then the parent dir.
+_swb_find_backend() {
+    local name="$1" p
+    for p in "$SCRIPT_DIR/$name" "$SCRIPT_DIR/../$name"; do
+        [ -f "$p" ] && { echo "$p"; return 0; }
+    done
+    return 1
+}
+
+# Source blanton_fpga_pcimem.sh (cb_fpga) + blanton_cb_i2c.sh (cb_pmbus_*).
+_swb_backend_load() {
+    local f
+    if ! declare -F cb_fpga >/dev/null 2>&1; then
+        if f=$(_swb_find_backend "blanton_fpga_pcimem.sh"); then
+            # shellcheck source=/dev/null
+            source "$f"
+            echo -e "[\033[34mINFO\033[0m] SWB backend: sourced $f"
+        else
+            echo -e "[\033[31mERRO\033[0m] blanton_fpga_pcimem.sh not found in $SCRIPT_DIR or its parent"
+            return 1
+        fi
+    fi
+    if ! declare -F cb_pmbus_read >/dev/null 2>&1; then
+        if f=$(_swb_find_backend "blanton_cb_i2c.sh"); then
+            # shellcheck source=/dev/null
+            source "$f" >/dev/null
+            echo -e "[\033[34mINFO\033[0m] SWB backend: sourced $f"
+        else
+            echo -e "[\033[31mERRO\033[0m] blanton_cb_i2c.sh not found in $SCRIPT_DIR or its parent"
+            return 1
+        fi
+    fi
+    declare -F cb_pmbus_read >/dev/null 2>&1 || {
+        echo -e "[\033[31mERRO\033[0m] cb_pmbus_read still undefined after sourcing the backend"; return 1; }
+    return 0
+}
+
+# Run a cb_* command with pcimem tracing suppressed (shared DEBUG_MODE var).
+# Echoes the command's stdout, preserves its return code.
+_swb_call() {
+    local _saved="$DEBUG_MODE" _rc
+    [ "$MARGIN_SWB_PCIMEM_DEBUG" = "1" ] || DEBUG_MODE=0
+    "$@"
+    _rc=$?
+    DEBUG_MODE="$_saved"
+    return $_rc
+}
+
+# Probe one LTC2977: 1-byte PMBus read of PAGE (0x00). Returns cb_pmbus_read's rc.
+_swb_probe_addr() {
+    _swb_call cb_pmbus_read "$CB_I2C_CH" "$1" 0x00 1 >/dev/null 2>&1
+}
+
+# --- SWB wire ops used by the transport switch below ------------------------
+# Both use _ADDR (LTC2977 7-bit slave) set by _get_chip and CB_I2C_CH from the
+# .conf. Unlike i2cset/i2cget these report failures: a NACK on the FPGA I2C
+# master used to silently turn into Vout=0.0000.
+
+# _swb_write <reg> <byte> [byte...]   -> cb_pmbus_write (LSB first for LINEAR16)
+_swb_write() {
+    local reg=$1; shift
+    [ "$DEBUG_MODE" = "1" ] && echo -e "\033[90m[DEBG] cb_pmbus_write $CB_I2C_CH $_ADDR $reg $*\033[0m"
+    if ! _swb_call cb_pmbus_write "$CB_I2C_CH" "$_ADDR" "$reg" "$@" >/dev/null 2>&1; then
+        echo -e "[\033[31mERRO\033[0m] cb_pmbus_write ch=$CB_I2C_CH $_ADDR reg=$reg failed (NACK/timeout)" >&2
+        _log_detail "ERRO cb_pmbus_write ch=$CB_I2C_CH $_ADDR $reg $*"
+        return 1
+    fi
+    return 0
+}
+
+# _swb_read_word <reg>  -> echoes "0xXXXX" parsed out of cb_pmbus_read's "=> 0xXXXX"
+_swb_read_word() {
+    local reg=$1 out word
+    [ "$DEBUG_MODE" = "1" ] && echo -e "\033[90m[DEBG] cb_pmbus_read $CB_I2C_CH $_ADDR $reg 2\033[0m" >&2
+    if ! out=$(_swb_call cb_pmbus_read "$CB_I2C_CH" "$_ADDR" "$reg" 2 2>/dev/null); then
+        echo -e "[\033[31mERRO\033[0m] cb_pmbus_read ch=$CB_I2C_CH $_ADDR reg=$reg failed (NACK/timeout)" >&2
+        _log_detail "ERRO cb_pmbus_read ch=$CB_I2C_CH $_ADDR $reg"
+        echo "0x0000"
+        return 1
+    fi
+    # cb_pmbus_read prints "  [PMB-R] ... => 0xXXXX  raw=[...] linear16=..."
+    word=$(printf '%s' "$out" | awk -F'=> ' 'NF>1{print $2}' | awk '{print $1}')
+    [[ "$word" =~ ^0[xX][0-9a-fA-F]+$ ]] || word="0x0000"
+    echo "$word"
+}
+
+# Bring up the FPGA I2C channel for this .conf: validate CB_I2C_CH, prescale +
+# enable it once (cb_i2c_init), optionally take the semaphore, then probe CHIPS.
+_swb_setup() {
+    _SWB_READY=0
+
+    if [ -z "$CB_I2C_CH" ]; then
+        echo -e "[\033[31mERRO\033[0m] TRANSPORT=swb but CB_I2C_CH is empty in the .conf"
+        return 1
+    fi
+    if ! [[ "$CB_I2C_CH" =~ ^[0-9]+$ ]] || [ "$CB_I2C_CH" -gt 17 ]; then
+        echo -e "[\033[31mERRO\033[0m] CB_I2C_CH='$CB_I2C_CH' invalid (CB F3 I2C channels are 0..17)"
+        return 1
+    fi
+    case " $MARGIN_SWB_CHANNELS " in
+        *" $CB_I2C_CH "*) ;;
+        *) echo -e "[\033[33mWARN\033[0m] CB_I2C_CH=$CB_I2C_CH is not a known SWB VRM channel ($MARGIN_SWB_CHANNELS)" ;;
+    esac
+
+    # Prescale + MOD_EN on this channel.
+    if ! _swb_call cb_i2c_init "$CB_I2C_CH" "$MARGIN_SWB_PRESCALE_LO" "$MARGIN_SWB_PRESCALE_HI"; then
+        echo -e "[\033[31mERRO\033[0m] cb_i2c_init $CB_I2C_CH failed (FPGA/pcimem access?)"
+        return 1
+    fi
+    CB_I2C_AUTO_INIT="$MARGIN_SWB_AUTO_INIT"
+    local _khz="?"; [ "$MARGIN_SWB_PRESCALE_LO" = "0x88" ] && _khz="100"
+    [ "$MARGIN_SWB_PRESCALE_LO" = "0x24" ] && _khz="400"
+    echo -e "[\033[34mINFO\033[0m] cb_i2c_init ch=$CB_I2C_CH prescale=$MARGIN_SWB_PRESCALE_LO/$MARGIN_SWB_PRESCALE_HI (~${_khz}kHz), CB_I2C_AUTO_INIT=$CB_I2C_AUTO_INIT"
+    _log "swb: cb_i2c_init ch=$CB_I2C_CH prescale=$MARGIN_SWB_PRESCALE_LO auto_init=$CB_I2C_AUTO_INIT"
+
+    if [ "$MARGIN_SWB_USE_SEM" = "1" ]; then
+        if _swb_call cb_i2c_sem "$CB_I2C_CH" acquire; then
+            _SWB_SEM_HELD=1
+        else
+            echo -e "[\033[33mWARN\033[0m] semaphore on ch=$CB_I2C_CH not acquired; continuing without it"
+        fi
+    fi
+
+    _SWB_READY=1
+
+    if [ "$MARGIN_SWB_PROBE" = "1" ]; then
+        local idx=0 chip addr bad=0
+        for chip in "${CHIPS[@]}"; do
+            IFS=':' read -r _ addr <<< "$chip"
+            if _swb_probe_addr "$addr"; then
+                echo -e "[\033[34mINFO\033[0m] probe ch=$CB_I2C_CH LTC2977[$idx] $addr : \033[32mACK\033[0m"
+            else
+                echo -e "[\033[33mWARN\033[0m] probe ch=$CB_I2C_CH LTC2977[$idx] $addr : \033[31mNACK\033[0m (wrong CB_I2C_CH / addr, board absent, or channel stuck -> margin_swb_scan / margin_swb_reset)"
+                bad=1
+            fi
+            idx=$((idx+1))
+        done
+        _log "swb: probe ch=$CB_I2C_CH chips=${CHIPS[*]} $( [ "$bad" = "0" ] && echo all-ACK || echo has-NACK )"
+    fi
+    return 0
+}
+
+# --- SWB debug / maintenance wrappers (thin shells over blanton_cb_i2c.sh) ---
+_swb_guard() {
+    if [ "$TRANSPORT" != "swb" ]; then
+        echo -e "[\033[33mWARN\033[0m] current setting is TRANSPORT=$TRANSPORT (not swb); nothing to do"
+        return 1
+    fi
+    declare -F cb_pmbus_read >/dev/null 2>&1 || { echo -e "[\033[31mERRO\033[0m] SWB backend not loaded; run margin_init first"; return 1; }
+    return 0
+}
+
+# margin_swb_info -- show the transport wiring of the loaded setting
+margin_swb_info() {
+    echo "-------------"
+    echo "[$PART_NUMBER] transport"
+    echo "-------------"
+    echo "  TRANSPORT   : $TRANSPORT"
+    if [ "$TRANSPORT" = "swb" ]; then
+        echo "  CB_I2C_CH   : $CB_I2C_CH  (CB FPGA F3, base $(printf '0x%X' $(( 0x300 + CB_I2C_CH * 0x20 ))))"
+        echo "  LTC2977     : ${CHIPS[*]}  (bus field unused on swb)"
+        echo "  prescale    : $MARGIN_SWB_PRESCALE_LO/$MARGIN_SWB_PRESCALE_HI   auto_init=$CB_I2C_AUTO_INIT   sem_held=$_SWB_SEM_HELD"
+        echo "  wire ops    : cb_pmbus_write $CB_I2C_CH <addr> 0x00 <page> / cb_pmbus_read $CB_I2C_CH <addr> 0x8b 2"
+    else
+        echo "  bus:addr    : ${CHIPS[*]}  (i2cset/i2cget)"
+    fi
+}
+
+# margin_swb_probe -- re-run the PAGE-read presence check on every LTC2977
+margin_swb_probe() {
+    _swb_guard || return 1
+    local idx=0 chip addr
+    for chip in "${CHIPS[@]}"; do
+        IFS=':' read -r _ addr <<< "$chip"
+        if _swb_probe_addr "$addr"; then
+            echo -e "  ch=$CB_I2C_CH $addr : \033[32mACK\033[0m"
+        else
+            echo -e "  ch=$CB_I2C_CH $addr : \033[31mNACK\033[0m"
+        fi
+        idx=$((idx+1))
+    done
+}
+
+# margin_swb_scan [ch] -- cb_i2c_scan on this conf's channel (0x08..0x77)
+margin_swb_scan() {
+    _swb_guard || return 1
+    _swb_call cb_i2c_scan "${1:-$CB_I2C_CH}"
+}
+
+# margin_swb_reset -- local I2C controller reset (0xD) + re-init, for a stuck bus
+margin_swb_reset() {
+    _swb_guard || return 1
+    _swb_call cb_i2c_reset "$CB_I2C_CH"
+    _swb_call cb_i2c_init "$CB_I2C_CH" "$MARGIN_SWB_PRESCALE_LO" "$MARGIN_SWB_PRESCALE_HI"
+    echo -e "[\033[34mINFO\033[0m] ch=$CB_I2C_CH reset + re-init done"
+    _log "swb: cb_i2c_reset + cb_i2c_init ch=$CB_I2C_CH"
+}
+
+# margin_swb_sem [status|acquire|release]
+margin_swb_sem() {
+    _swb_guard || return 1
+    local act="${1:-status}"
+    _swb_call cb_i2c_sem "$CB_I2C_CH" "$act"
+    case "$act" in
+        acquire) _SWB_SEM_HELD=1 ;;
+        release) _SWB_SEM_HELD=0 ;;
+    esac
+}
+
+# margin_swb_sem_release -- release the session semaphore if margin_init took it
+margin_swb_sem_release() {
+    [ "$_SWB_SEM_HELD" = "1" ] || { echo -e "[\033[34mINFO\033[0m] no semaphore held by this session"; return 0; }
+    _swb_call cb_i2c_sem "$CB_I2C_CH" release
+    _SWB_SEM_HELD=0
+}
+
+# --- Init: load setting by name ---
+margin_init() {
+    if [ -z "$1" ]; then
+        echo -e "[\033[31mERRO\033[0m] Usage: margin_init <PART_NUMBER>"
+        return 1
+    fi
+    PART_NUMBER="$1"
+    echo "Part Number: $PART_NUMBER"
+
+    local setting_file="$SETTINGS_DIR/${PART_NUMBER}.conf"
+    if [ ! -f "$setting_file" ]; then
+        echo -e "[\033[31mERRO\033[0m] Setting file not found: $setting_file"
+        return 1
+    fi
+    TRANSPORT="i2c"; CB_I2C_CH=""   # reset before sourcing; swb confs override
+    source "$setting_file"
+    TRANSPORT="${TRANSPORT:-i2c}"    # a blank TRANSPORT="" in a .conf means i2c
+    echo -e "[\033[34mINFO\033[0m] Loaded setting: $setting_file (transport=$TRANSPORT)"
+
+    # SWB rails need the cb_pmbus_* backend (blanton_cb_i2c.sh + blanton_fpga_pcimem.sh,
+    # normally in the parent Blanton_Script/ dir); load it and bring the FPGA I2C
+    # channel up once. CB/i2c settings skip this entirely.
+    _SWB_READY=0; _SWB_SEM_HELD=0
+    if [ "$TRANSPORT" = "swb" ]; then
+        _swb_backend_load || return 1
+        _swb_setup || return 1
+    fi
+    _log_start_session
+}
+
+# --- Tab completion for margin_init ---
+_margin_init_completions() {
+    [ "$COMP_CWORD" -ne 1 ] && return
+    local cur="${COMP_WORDS[COMP_CWORD]}"
+    local names=$(ls "$SETTINGS_DIR"/*.conf 2>/dev/null | xargs -n1 basename | sed 's/\.conf$//')
+    COMPREPLY=($(compgen -W "$names" -- "$cur"))
+}
+complete -F _margin_init_completions margin_init
+
+# --- PRE/POST scope helpers ---
+# PRE/POST run once at the outermost public-function entry/exit.
+# Nested calls (e.g. margin_apply_profile -> margin_set -> margin_read_vout)
+# see _PRE_SCOPE already set and skip, so the mux only switches once.
+_run_cmds() {
+    local cmds=$1 label=$2
+    [ -z "$cmds" ] && return
+    IFS=';' read -ra _cmds <<< "$cmds"
+    for _cmd in "${_cmds[@]}"; do
+        _cmd=$(echo "$_cmd" | xargs)
+        [ -z "$_cmd" ] && continue
+        [ "$DEBUG_MODE" = "1" ] && echo -e "\033[36m$label $_cmd\033[0m"
+        eval "$_cmd" >/dev/null 2>&1
+    done
+}
+
+# Returns 0 (true) if caller owns the scope and must call _pre_exit on the way out.
+_pre_enter_own() {
+    if [ -z "$_PRE_SCOPE" ]; then
+        _PRE_SCOPE=1
+        _run_cmds "${CHIP_PRE_CMD[0]}" "[PRE]"
+        return 0
+    fi
+    return 1
+}
+
+_pre_exit() {
+    _run_cmds "${CHIP_POST_CMD[0]}" "[POST]"
+    _PRE_SCOPE=""
+}
+
+# --- Helper: set _BUS and _ADDR from channel number ---
+# Both transports use CHIPS (LTC2977 addresses). For swb the bus field is unused
+# (the FPGA I2C channel comes from CB_I2C_CH); _ADDR is the PMBus slave.
+_get_chip() {
+    local chip_idx=$(( $1 / 8 ))
+    IFS=':' read -r _BUS _ADDR <<< "${CHIPS[$chip_idx]}"
+}
+
+# --- Helper: get page (channel within LTC2977, 0x00~0x07) ---
+_get_page() {
+    printf "0x%02x" $(( $1 % 8 ))
+}
+
+# --- I2C low-level helpers (use _BUS/_ADDR set by _get_chip) ---
+# TRANSPORT=swb swaps the i2cset/i2cget wire op for cb_pmbus_* on CB_I2C_CH.
+# PAGE is written the same way on both (PMBus command 0x00).
+_open_page() {
+    if [ "$TRANSPORT" = "swb" ]; then
+        _swb_write 0x00 "$1"
+        return
+    fi
+    [ "$DEBUG_MODE" = "1" ] && echo -e "\033[90m[DEBG] i2cset -y $_BUS $_ADDR 0x00 $1 b\033[0m"
+    i2cset -y "$_BUS" "$_ADDR" 0x00 "$1" b >/dev/null 2>&1
+}
+
+# Write a 16-bit word (LINEAR16, little-endian: lo byte first).
+_i2c_write_word() {
+    local reg=$1 lo=$2 hi=$3
+    if [ "$TRANSPORT" = "swb" ]; then
+        _swb_write "$reg" "$lo" "$hi"
+        return
+    fi
+    local word=$(( (hi << 8) | lo ))
+    local word_hex=$(printf "0x%04x" "$word")
+    [ "$DEBUG_MODE" = "1" ] && echo -e "\033[90m[DEBG] i2cset -y $_BUS $_ADDR $reg $word_hex w\033[0m"
+    i2cset -y "$_BUS" "$_ADDR" "$reg" "$word" w >/dev/null 2>&1
+}
+
+_i2c_write_byte() {
+    if [ "$TRANSPORT" = "swb" ]; then
+        _swb_write "$1" "$2"
+        return
+    fi
+    [ "$DEBUG_MODE" = "1" ] && echo -e "\033[90m[DEBG] i2cset -y $_BUS $_ADDR $1 $2 b\033[0m"
+    i2cset -y "$_BUS" "$_ADDR" "$1" "$2" b >/dev/null 2>&1
+}
+
+# Read a 16-bit word; echoes "0xXXXX". For swb, parse cb_pmbus_read's "=> 0xXXXX".
+_i2c_read_word() {
+    if [ "$TRANSPORT" = "swb" ]; then
+        _swb_read_word "$1"
+        return
+    fi
+    [ "$DEBUG_MODE" = "1" ] && echo -e "\033[90m[DEBG] i2cget -y $_BUS $_ADDR $1 w\033[0m" >&2
+    local result
+    result=$(i2cget -y "$_BUS" "$_ADDR" "$1" w 2>/dev/null)
+    if [ -z "$result" ]; then
+        echo "0x0000"
+    else
+        echo "$result"
+    fi
+}
+
+# --- Enable current channel for margining (clear ON_OFF_CONFIG use_control) ---
+# Assumes _get_chip + _open_page already ran (uses current _BUS/_ADDR/page).
+# Lets a subsequent OPERATION command turn the channel on so the servo DAC
+# soft-connects; without this, rails the LTC2980 doesn't sequence stay OFF and
+# margining has no effect. RAM-only; a power cycle restores the stored value.
+_enable_channel() {
+    _i2c_write_byte 0x02 "$ONOFF_ENABLE_VALUE"
+}
+
+# --- Helper: decimal to LINEAR16 (returns "lo hi" hex strings) ---
+_dec_to_lin16() {
+    local value=$1
+    if [ "$value" = "0" ]; then
+        echo "0x00 0x00"
+        return
+    fi
+    local raw=$(awk "BEGIN { printf \"%04X\", int($value * 8192) }")
+    local hi=${raw:0:2}
+    local lo=${raw:2:2}
+    echo "0x${lo} 0x${hi}"
+}
+
+# --- Helper: LINEAR16 word to decimal voltage ---
+# i2cget returns a hex string like "0x9fc2". SONiC's awk (busybox/mawk) does NOT
+# parse a "0x" prefix in arithmetic and treats it as 0, so convert hex -> decimal
+# with bash arithmetic $(( )) first, then feed the decimal to awk.
+_lin16_to_dec() {
+    local raw_word=$(( ${1:-0} ))
+    awk "BEGIN { printf \"%.4f\", $raw_word / 8192.0 }"
+}
+
+# --- Read Vout for a channel ---
+margin_read_vout() {
+    local ch=$1
+    local vnom_var="CH${ch}_VNOM"
+    local net_var="CH${ch}_NET"
+    local vnom=${!vnom_var}
+    local net=${!net_var}
+
+    if [ "$vnom" = "-" ] || [ -z "$vnom" ]; then
+        printf "CH %2d: Channel not used\n" "$ch"
+        LAST_VOUT="0"
+        return
+    fi
+
+    local _own=0
+    _pre_enter_own && _own=1
+
+    _get_chip "$ch"
+    _open_page "$(_get_page "$ch")"
+    local raw
+    raw=$(_i2c_read_word 0x8b)
+    local vout=$(_lin16_to_dec "$raw")
+
+    local pct
+    pct=$(awk "BEGIN { printf \"%+.3f\", ($vout - $vnom) / $vnom * 100 }")
+    local _line
+    printf -v _line "CH %2d: Vnom = %.3f, Vout = %s (%s%%). Net - %s" "$ch" "$vnom" "$vout" "$pct" "$net"
+    echo "$_line"
+    _log_detail "$_line"
+    LAST_VOUT="$vout"
+
+    [ "$_own" = "1" ] && _pre_exit
+}
+
+# --- Status: read all or specific channel ---
+margin_status() {
+    local ch_in=${1:-all}
+    echo "-------------"
+    echo "[$PART_NUMBER] Channel status"
+    echo "-------------"
+    _log_label "margin_status [$PART_NUMBER] ch=$ch_in"
+
+    local _own=0
+    _pre_enter_own && _own=1
+
+    if [ "$ch_in" = "all" ]; then
+        for i in $(seq 0 15); do
+            local vnom_var="CH${i}_VNOM"
+            [ -n "${!vnom_var}" ] && margin_read_vout "$i"
+        done
+    else
+        margin_read_vout "$ch_in"
+    fi
+
+    [ "$_own" = "1" ] && _pre_exit
+}
+
+# --- Set margin value (write high/low + OV/UV) ---
+margin_set_value() {
+    local ch=$1 vnom=$2 change=$3 ovuv=${4:-2}
+
+    local high_val low_val ov_val uv_val
+    high_val=$(_dec_to_lin16 "$(awk "BEGIN { print $vnom * (1 + $change/100) }")")
+    low_val=$(_dec_to_lin16 "$(awk "BEGIN { print $vnom * (1 - $change/100) }")")
+    ov_val=$(_dec_to_lin16 "$(awk "BEGIN { print $vnom * (1 + ($change+$ovuv)/100) }")")
+    uv_val=$(_dec_to_lin16 "$(awk "BEGIN { print $vnom * (1 - ($change+$ovuv)/100) }")")
+
+    local _own=0
+    _pre_enter_own && _own=1
+
+    _get_chip "$ch"
+    _open_page "$(_get_page "$ch")"
+
+    local hi lo
+    read lo hi <<< $high_val
+    _i2c_write_word 0x25 "$lo" "$hi"
+    read lo hi <<< $low_val
+    _i2c_write_word 0x26 "$lo" "$hi"
+    read lo hi <<< $ov_val
+    _i2c_write_word 0x40 "$lo" "$hi"
+    read lo hi <<< $uv_val
+    _i2c_write_word 0x44 "$lo" "$hi"
+
+    [ "$_own" = "1" ] && _pre_exit
+}
+
+# --- Set operation register ---
+margin_operation() {
+    local ch=$1 op=$2
+
+    local op_val
+    case "$op" in
+        high)    op_val=0xa8 ;;
+        low)     op_val=0x98 ;;
+        nominal) op_val=0x80 ;;
+        off)     op_val=0x00 ;;
+        *)       echo -e "[\033[31mERRO\033[0m] invalid operation '$op'"; return 1 ;;
+    esac
+
+    local _own=0
+    _pre_enter_own && _own=1
+
+    _get_chip "$ch"
+    _open_page "$(_get_page "$ch")"
+    # Let OPERATION turn the channel on (soft-connect DAC) even on rails the
+    # LTC2980 does not sequence; skip when turning the channel off.
+    [ "$MARGIN_AUTO_ENABLE" = "1" ] && [ "$op" != "off" ] && _enable_channel
+    _i2c_write_byte 0x01 "$op_val"
+    sleep "$MARGIN_SETTLE"
+
+    [ "$_own" = "1" ] && _pre_exit
+}
+
+# --- Set: combined set_value + operation + verify ---
+margin_set() {
+    local ch=$1 op=$2 change=$3
+    local vnom_var="CH${ch}_VNOM"
+    local vnom=${!vnom_var}
+
+    if [ "$vnom" = "-" ] || [ -z "$vnom" ]; then
+        printf "CH %2d: Channel not used\n" "$ch"
+        return
+    fi
+
+    local _own=0
+    _pre_enter_own && _own=1
+
+    margin_set_value "$ch" "$vnom" "$change"
+    margin_operation "$ch" "$op"
+    margin_read_vout "$ch"
+    local _line
+    printf -v _line "CH %2d: Set %s %s%% done (Vout=%s)" "$ch" "$op" "$change" "$LAST_VOUT"
+    echo "$_line"
+    _log_detail "$_line"
+    _log "$(printf 'margin_set CH%2d %-7s %3s%% Vout=%-8s' $ch $op $change $LAST_VOUT)\033[90m(detail Line:${_LOG_DETAIL_LINE})\033[0m"
+
+    [ "$_own" = "1" ] && _pre_exit
+}
+
+# --- Apply a margin profile file ---
+margin_apply_profile() {
+    local profile=${1:-"$PROFILES_DIR/${PART_NUMBER}_default.conf"}
+    if [ ! -f "$profile" ]; then
+        echo -e "[\033[31mERRO\033[0m] Profile not found: $profile"
+        return 1
+    fi
+    echo "Applying profile: $profile"
+    _log_label "margin_apply_profile [$PART_NUMBER] $profile"
+    source "$profile"
+
+    local _own=0
+    _pre_enter_own && _own=1
+
+    for entry in "${PROFILE_CHANNELS[@]}"; do
+        local ch op change
+        IFS=':' read -r ch op change <<< "$entry"
+        margin_set "$ch" "$op" "$change"
+    done
+
+    [ "$_own" = "1" ] && _pre_exit
+}
+
+# --- Save to NVM ---
+margin_save() {
+    local _own=0
+    _pre_enter_own && _own=1
+
+    for chip in "${CHIPS[@]}"; do
+        IFS=':' read -r _BUS _ADDR <<< "$chip"
+        _i2c_write_byte 0x15 0x00
+    done
+    echo "Change Saved (${#CHIPS[@]} chips)"
+    _log_label "margin_save $PART_NUMBER (${#CHIPS[@]} chips)"
+
+    [ "$_own" = "1" ] && _pre_exit
+}
+
+if [ -z "$_LOG_FILE" ]; then
+    _LOG_FILE="$LOGS_DIR/margin_$(date '+%Y%m%d_%H%M%S').log"
+    _LOG_DETAIL_FILE="${_LOG_FILE%.log}_detail.log"
+    _log "=== Session start ==="
+    _log "Detail log: $_LOG_DETAIL_FILE"
+fi
+
+echo -e "[\033[34mINFO\033[0m] LTC2980 Margin Tool loaded. Run 'margin_init' to start."
diff --git a/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_CB_CONN13.conf b/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_CB_CONN13.conf
index 478d899..5326c51 100644
--- a/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_CB_CONN13.conf
+++ b/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_CB_CONN13.conf
@@ -1,52 +1,52 @@
-# Blanton Channel Settings
-# Format: CH<n>_VNOM=voltage  CH<n>_NET=net_name
-#
-# Channel numbering (Script Channel, per Blanton_Margin_List):
-#   ch_global / 8 -> CHIPS index (0~17)
-#   ch_global % 8 -> page within LTC2977 (0~7)
-# One LTC2980 = two LTC2977 (8ch each), controlled via 2 I2C addresses.
-
-# --- Transport (blank = i2c): CB's LTC2980 is on the native I2C bus, driven by
-#     i2cset/i2cget. Only SWB boards set TRANSPORT="swb" + CB_I2C_CH=<6|7|8|9>. ---
-TRANSPORT=""
-CB_I2C_CH=
-
-# --- I2C Configuration ---
-
-# Format: "bus:address"  (8 channels per entry / per LTC2977)
-CHIPS=(
-    # chip1: CB (CONN13)
-    "4:0x5C"    # CH0   ~ CH7
-    "4:0x5E"    # CH8   ~ CH15
-)
-
-# Pre-commands to run before accessing each chip (empty = none)
-# Multiple commands separated by ;
-CHIP_PRE_CMD=(
-    ""    # CB     CONN13 (lo)
-)
-
-# Post-commands to run after accessing each chip (optional, empty = none)
-CHIP_POST_CMD=(
-    ""    # CB     CONN13 (lo)
-)
-
-# ============================================================
-# chip1: CB (CONN13)
-# ============================================================
-CH0_VNOM="5.0";     CH0_NET="V5P0_ALW"
-CH1_VNOM="3.3";     CH1_NET="V3P3_ALW"
-CH2_VNOM="0.75";    CH2_NET="PWR_VDD_MISC_ALW"
-CH3_VNOM="1.8";     CH3_NET="V1P8_ALW"
-CH4_VNOM="1.1";     CH4_NET="PWR_APU_VDDIO_SUS"
-CH5_VNOM="0.75";    CH5_NET="PWR_VDD_MISC_RUN"
-CH6_VNOM="0.78";    CH6_NET="PWR_APU_VDD_MEM_RUN"
-CH7_VNOM="0.8";     CH7_NET="V0P8_PHY2_DVDD"
-CH8_VNOM="0.8";     CH8_NET="V0P8_AVDD"
-CH9_VNOM="0.8";     CH9_NET="V0P8_PHY"
-CH10_VNOM="1.8";    CH10_NET="V1P8_FPGA"
-CH11_VNOM="2.5";    CH11_NET="V2P5_FPGA"
-CH12_VNOM="1.1";    CH12_NET="V1P1_FPGA"
-CH13_VNOM="5.0";    CH13_NET="P5V_STBY"
-CH14_VNOM="3.3";    CH14_NET="P3V3_STBY"
-CH15_VNOM="0.8";    CH15_NET="V0P8_PHY2_AVDD"
+# Blanton Channel Settings
+# Format: CH<n>_VNOM=voltage  CH<n>_NET=net_name
+#
+# Channel numbering (Script Channel, per Blanton_Margin_List):
+#   ch_global / 8 -> CHIPS index (0~17)
+#   ch_global % 8 -> page within LTC2977 (0~7)
+# One LTC2980 = two LTC2977 (8ch each), controlled via 2 I2C addresses.
+
+# --- Transport (blank = i2c): CB's LTC2980 is on the native I2C bus, driven by
+#     i2cset/i2cget. Only SWB boards set TRANSPORT="swb" + CB_I2C_CH=<6|7|8|9>. ---
+TRANSPORT=""
+CB_I2C_CH=
+
+# --- I2C Configuration ---
+
+# Format: "bus:address"  (8 channels per entry / per LTC2977)
+CHIPS=(
+    # chip1: CB (CONN13)
+    "4:0x5C"    # CH0   ~ CH7
+    "4:0x5E"    # CH8   ~ CH15
+)
+
+# Pre-commands to run before accessing each chip (empty = none)
+# Multiple commands separated by ;
+CHIP_PRE_CMD=(
+    ""    # CB     CONN13 (lo)
+)
+
+# Post-commands to run after accessing each chip (optional, empty = none)
+CHIP_POST_CMD=(
+    ""    # CB     CONN13 (lo)
+)
+
+# ============================================================
+# chip1: CB (CONN13)
+# ============================================================
+CH0_VNOM="5.0";     CH0_NET="V5P0_ALW"
+CH1_VNOM="3.3";     CH1_NET="V3P3_ALW"
+CH2_VNOM="0.75";    CH2_NET="PWR_VDD_MISC_ALW"
+CH3_VNOM="1.8";     CH3_NET="V1P8_ALW"
+CH4_VNOM="1.1";     CH4_NET="PWR_APU_VDDIO_SUS"
+CH5_VNOM="0.75";    CH5_NET="PWR_VDD_MISC_RUN"
+CH6_VNOM="0.78";    CH6_NET="PWR_APU_VDD_MEM_RUN"
+CH7_VNOM="0.8";     CH7_NET="V0P8_PHY2_DVDD"
+CH8_VNOM="0.8";     CH8_NET="V0P8_AVDD"
+CH9_VNOM="0.8";     CH9_NET="V0P8_PHY"
+CH10_VNOM="1.8";    CH10_NET="V1P8_FPGA"
+CH11_VNOM="2.5";    CH11_NET="V2P5_FPGA"
+CH12_VNOM="1.1";    CH12_NET="V1P1_FPGA"
+CH13_VNOM="5.0";    CH13_NET="P5V_STBY"
+CH14_VNOM="3.3";    CH14_NET="P3V3_STBY"
+CH15_VNOM="0.8";    CH15_NET="V0P8_PHY2_AVDD"
diff --git a/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN13.conf b/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN13.conf
index 509206d..0e4b344 100644
--- a/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN13.conf
+++ b/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN13.conf
@@ -1,52 +1,52 @@
-# Blanton Channel Settings
-# Format: CH<n>_VNOM=voltage  CH<n>_NET=net_name
-#
-# Channel numbering (Script Channel, per Blanton_Margin_List):
-#   ch_global / 8 -> CHIPS index (0~17)
-#   ch_global % 8 -> page within LTC2977 (0~7)
-# One LTC2980 = two LTC2977 (8ch each), controlled via 2 I2C addresses.
-
-# --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
-#     it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
-TRANSPORT="swb"
-CB_I2C_CH=6           # CB F3 Ch6 = SWB0 CONN13/CONN14 (shared with CONN14, addr must differ)
-
-# --- I2C Configuration ---
-
-# Format: "bus:address"  (8 channels per entry / per LTC2977)
-CHIPS=(
-    # chip1: SWB0 (CONN13)
-    "0:0x5C"    # CH0   ~ CH7
-    "0:0x5E"    # CH8   ~ CH15
-)
-
-# Pre-commands to run before accessing each chip (empty = none)
-# Multiple commands separated by ;
-CHIP_PRE_CMD=(
-    ""    # SWB0   CONN13 (lo)
-)
-
-# Post-commands to run after accessing each chip (optional, empty = none)
-CHIP_POST_CMD=(
-    ""    # SWB0   CONN13 (lo)
-)
-
-# ============================================================
-# chip1: SWB0 (CONN13)
-# ============================================================
-CH0_VNOM="0.75";    CH0_NET="P0V75_DVDD_47"
-CH1_VNOM="0.75";    CH1_NET="P0V75_AVDD_47"
-CH2_VNOM="1.5";     CH2_NET="P1V5_AVDD_47"
-CH3_VNOM="0.9";     CH3_NET="P0V9_AVDD_47"
-CH4_VNOM="1.8";     CH4_NET="P1V8_1"
-CH5_VNOM="3.3";     CH5_NET="PVDD3_3V_SYNTH_LDO_A3"
-CH6_VNOM="3.3";     CH6_NET="PVDD3_3V_SYNTH_LDO_B1"
-CH7_VNOM="1.8";     CH7_NET="P1V8_3"
-CH8_VNOM="1.8";     CH8_NET="P1V8_DVDDIO_3"
-CH9_VNOM="0.75";    CH9_NET="P0V75_DVDD_39"
-CH10_VNOM="0.75";   CH10_NET="P0V75_AVDD_39"
-CH11_VNOM="1.5";    CH11_NET="P1V5_AVDD_39"
-CH12_VNOM="0.9";    CH12_NET="P0V9_AVDD_39"
-CH13_VNOM="1.5";    CH13_NET="PVDD1V5_2"
-CH14_VNOM="1.8";    CH14_NET="PVDD1V8_DUT"
-CH15_VNOM="1.2";    CH15_NET="PVDD_MDIO"
+# Blanton Channel Settings
+# Format: CH<n>_VNOM=voltage  CH<n>_NET=net_name
+#
+# Channel numbering (Script Channel, per Blanton_Margin_List):
+#   ch_global / 8 -> CHIPS index (0~17)
+#   ch_global % 8 -> page within LTC2977 (0~7)
+# One LTC2980 = two LTC2977 (8ch each), controlled via 2 I2C addresses.
+
+# --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
+#     it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
+TRANSPORT="swb"
+CB_I2C_CH=6           # CB F3 Ch6 = SWB0 CONN13/CONN14 (shared with CONN14, addr must differ)
+
+# --- I2C Configuration ---
+
+# Format: "bus:address"  (8 channels per entry / per LTC2977)
+CHIPS=(
+    # chip1: SWB0 (CONN13)
+    "0:0x5C"    # CH0   ~ CH7
+    "0:0x5E"    # CH8   ~ CH15
+)
+
+# Pre-commands to run before accessing each chip (empty = none)
+# Multiple commands separated by ;
+CHIP_PRE_CMD=(
+    ""    # SWB0   CONN13 (lo)
+)
+
+# Post-commands to run after accessing each chip (optional, empty = none)
+CHIP_POST_CMD=(
+    ""    # SWB0   CONN13 (lo)
+)
+
+# ============================================================
+# chip1: SWB0 (CONN13)
+# ============================================================
+CH0_VNOM="0.75";    CH0_NET="P0V75_DVDD_47"
+CH1_VNOM="0.75";    CH1_NET="P0V75_AVDD_47"
+CH2_VNOM="1.5";     CH2_NET="P1V5_AVDD_47"
+CH3_VNOM="0.9";     CH3_NET="P0V9_AVDD_47"
+CH4_VNOM="1.8";     CH4_NET="P1V8_1"
+CH5_VNOM="3.3";     CH5_NET="PVDD3_3V_SYNTH_LDO_A3"
+CH6_VNOM="3.3";     CH6_NET="PVDD3_3V_SYNTH_LDO_B1"
+CH7_VNOM="1.8";     CH7_NET="P1V8_3"
+CH8_VNOM="1.8";     CH8_NET="P1V8_DVDDIO_3"
+CH9_VNOM="0.75";    CH9_NET="P0V75_DVDD_39"
+CH10_VNOM="0.75";   CH10_NET="P0V75_AVDD_39"
+CH11_VNOM="1.5";    CH11_NET="P1V5_AVDD_39"
+CH12_VNOM="0.9";    CH12_NET="P0V9_AVDD_39"
+CH13_VNOM="1.5";    CH13_NET="PVDD1V5_2"
+CH14_VNOM="1.8";    CH14_NET="PVDD1V8_DUT"
+CH15_VNOM="1.2";    CH15_NET="PVDD_MDIO"
diff --git a/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN14.conf b/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN14.conf
index 8cad194..39f95e2 100644
--- a/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN14.conf
+++ b/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN14.conf
@@ -1,52 +1,52 @@
-# Blanton Channel Settings
-# Format: CH<n>_VNOM=voltage  CH<n>_NET=net_name
-#
-# Channel numbering (Script Channel, per Blanton_Margin_List):
-#   ch_global / 8 -> CHIPS index (0~17)
-#   ch_global % 8 -> page within LTC2977 (0~7)
-# One LTC2980 = two LTC2977 (8ch each), controlled via 2 I2C addresses.
-
-# --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
-#     it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
-TRANSPORT="swb"
-CB_I2C_CH=6           # CB F3 Ch6 = SWB0 CONN13/CONN14 (shared with CONN13, addr must differ)
-
-# --- I2C Configuration ---
-
-# Format: "bus:address"  (8 channels per entry / per LTC2977)
-CHIPS=(
-    # chip1: SWB0 (CONN14)
-    "0:0x5E"    # CH0   ~ CH7
-    "0:0x5F"    # CH8   ~ CH15
-)
-
-# Pre-commands to run before accessing each chip (empty = none)
-# Multiple commands separated by ;
-CHIP_PRE_CMD=(
-    ""    # SWB0   CONN14 (lo)
-)
-
-# Post-commands to run after accessing each chip (optional, empty = none)
-CHIP_POST_CMD=(
-    ""    # SWB0   CONN14 (lo)
-)
-
-# ============================================================
-# chip1: SWB0 (CONN14)
-# ============================================================
-CH0_VNOM="0.75";    CH0_NET="P0V75_AVDD_7"
-CH1_VNOM="1.5";     CH1_NET="P1V5_AVDD_7"
-CH2_VNOM="0.9";     CH2_NET="P0V9_AVDD_7"
-CH3_VNOM="1.8";     CH3_NET="P1V8_5"
-CH4_VNOM="1.8";     CH4_NET="P1V8_2"
-CH5_VNOM="3.3";     CH5_NET="PVDD3_3V_SYNTH_LDO_B2"
-CH6_VNOM="3.3";     CH6_NET="PVDD3_3V_SYNTH_LDO_A2"
-CH7_VNOM="3.3";     CH7_NET="PVDD3_3V_SYNTH_LDO_A1"
-CH8_VNOM="1.5";     CH8_NET="PVDD1V5_TSC"
-CH9_VNOM="1.5";     CH9_NET="PVDD1V5_ANLG"
-CH10_VNOM="-";      CH10_NET="NC"
-CH11_VNOM="-";      CH11_NET="NC"
-CH12_VNOM="1.5";    CH12_NET="PVDD1V5_1"
-CH13_VNOM="-";      CH13_NET="NC"
-CH14_VNOM="1.8";    CH14_NET="P1V8_DVDDIO_1"
-CH15_VNOM="0.75";   CH15_NET="P0V75_DVDD_7"
+# Blanton Channel Settings
+# Format: CH<n>_VNOM=voltage  CH<n>_NET=net_name
+#
+# Channel numbering (Script Channel, per Blanton_Margin_List):
+#   ch_global / 8 -> CHIPS index (0~17)
+#   ch_global % 8 -> page within LTC2977 (0~7)
+# One LTC2980 = two LTC2977 (8ch each), controlled via 2 I2C addresses.
+
+# --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
+#     it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
+TRANSPORT="swb"
+CB_I2C_CH=6           # CB F3 Ch6 = SWB0 CONN13/CONN14 (shared with CONN13, addr must differ)
+
+# --- I2C Configuration ---
+
+# Format: "bus:address"  (8 channels per entry / per LTC2977)
+CHIPS=(
+    # chip1: SWB0 (CONN14)
+    "0:0x5E"    # CH0   ~ CH7
+    "0:0x5F"    # CH8   ~ CH15
+)
+
+# Pre-commands to run before accessing each chip (empty = none)
+# Multiple commands separated by ;
+CHIP_PRE_CMD=(
+    ""    # SWB0   CONN14 (lo)
+)
+
+# Post-commands to run after accessing each chip (optional, empty = none)
+CHIP_POST_CMD=(
+    ""    # SWB0   CONN14 (lo)
+)
+
+# ============================================================
+# chip1: SWB0 (CONN14)
+# ============================================================
+CH0_VNOM="0.75";    CH0_NET="P0V75_AVDD_7"
+CH1_VNOM="1.5";     CH1_NET="P1V5_AVDD_7"
+CH2_VNOM="0.9";     CH2_NET="P0V9_AVDD_7"
+CH3_VNOM="1.8";     CH3_NET="P1V8_5"
+CH4_VNOM="1.8";     CH4_NET="P1V8_2"
+CH5_VNOM="3.3";     CH5_NET="PVDD3_3V_SYNTH_LDO_B2"
+CH6_VNOM="3.3";     CH6_NET="PVDD3_3V_SYNTH_LDO_A2"
+CH7_VNOM="3.3";     CH7_NET="PVDD3_3V_SYNTH_LDO_A1"
+CH8_VNOM="1.5";     CH8_NET="PVDD1V5_TSC"
+CH9_VNOM="1.5";     CH9_NET="PVDD1V5_ANLG"
+CH10_VNOM="-";      CH10_NET="NC"
+CH11_VNOM="-";      CH11_NET="NC"
+CH12_VNOM="1.5";    CH12_NET="PVDD1V5_1"
+CH13_VNOM="-";      CH13_NET="NC"
+CH14_VNOM="1.8";    CH14_NET="P1V8_DVDDIO_1"
+CH15_VNOM="0.75";   CH15_NET="P0V75_DVDD_7"
diff --git a/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN15.conf b/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN15.conf
index 9c707ca..dc018fe 100644
--- a/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN15.conf
+++ b/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN15.conf
@@ -1,52 +1,52 @@
-# Blanton Channel Settings
-# Format: CH<n>_VNOM=voltage  CH<n>_NET=net_name
-#
-# Channel numbering (Script Channel, per Blanton_Margin_List):
-#   ch_global / 8 -> CHIPS index (0~17)
-#   ch_global % 8 -> page within LTC2977 (0~7)
-# One LTC2980 = two LTC2977 (8ch each), controlled via 2 I2C addresses.
-
-# --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
-#     it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
-TRANSPORT="swb"
-CB_I2C_CH=8           # CB F3 Ch8 = SWB0 CONN15/CONN16 (shared with CONN16, addr must differ)
-
-# --- I2C Configuration ---
-
-# Format: "bus:address"  (8 channels per entry / per LTC2977)
-CHIPS=(
-    # chip1: SWB0 (CONN15)
-    "0:0x62"    # CH0   ~ CH7
-    "0:0x63"    # CH8   ~ CH15
-)
-
-# Pre-commands to run before accessing each chip (empty = none)
-# Multiple commands separated by ;
-CHIP_PRE_CMD=(
-    ""    # SWB0   CONN15 (lo)
-)
-
-# Post-commands to run after accessing each chip (optional, empty = none)
-CHIP_POST_CMD=(
-    ""    # SWB0   CONN15 (lo)
-)
-
-# ============================================================
-# chip1: SWB0 (CONN15)
-# ============================================================
-CH0_VNOM="1.5";     CH0_NET="P1V5_AVDD_55"
-CH1_VNOM="0.9";     CH1_NET="P0V9_AVDD_55"
-CH2_VNOM="0.75";    CH2_NET="P0V75_DVDD_63"
-CH3_VNOM="0.75";    CH3_NET="P0V75_AVDD_63"
-CH4_VNOM="1.5";     CH4_NET="P1V5_AVDD_63"
-CH5_VNOM="0.9";     CH5_NET="P0V9_AVDD_63"
-CH6_VNOM="3.3";     CH6_NET="PVDD3_3V_SYNTH_LDO_B3"
-CH7_VNOM="1.5";     CH7_NET="PVDD1V5_3"
-CH8_VNOM="0.85";    CH8_NET="P0V85_STBY"
-CH9_VNOM="1.8";     CH9_NET="P1V8_STBY"
-CH10_VNOM="-";      CH10_NET="NC"
-CH11_VNOM="3.3";    CH11_NET="P3V3_STBY"
-CH12_VNOM="0.9";    CH12_NET="PVDD0V9_2"
-CH13_VNOM="0.75";   CH13_NET="P0V75_DVDD_55"
-CH14_VNOM="0.75";   CH14_NET="P0V75_AVDD_55"
-CH15_VNOM="1.8";    CH15_NET="P1V8_DVDDIO_4"
+# Blanton Channel Settings
+# Format: CH<n>_VNOM=voltage  CH<n>_NET=net_name
+#
+# Channel numbering (Script Channel, per Blanton_Margin_List):
+#   ch_global / 8 -> CHIPS index (0~17)
+#   ch_global % 8 -> page within LTC2977 (0~7)
+# One LTC2980 = two LTC2977 (8ch each), controlled via 2 I2C addresses.
+
+# --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
+#     it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
+TRANSPORT="swb"
+CB_I2C_CH=8           # CB F3 Ch8 = SWB0 CONN15/CONN16 (shared with CONN16, addr must differ)
+
+# --- I2C Configuration ---
+
+# Format: "bus:address"  (8 channels per entry / per LTC2977)
+CHIPS=(
+    # chip1: SWB0 (CONN15)
+    "0:0x62"    # CH0   ~ CH7
+    "0:0x63"    # CH8   ~ CH15
+)
+
+# Pre-commands to run before accessing each chip (empty = none)
+# Multiple commands separated by ;
+CHIP_PRE_CMD=(
+    ""    # SWB0   CONN15 (lo)
+)
+
+# Post-commands to run after accessing each chip (optional, empty = none)
+CHIP_POST_CMD=(
+    ""    # SWB0   CONN15 (lo)
+)
+
+# ============================================================
+# chip1: SWB0 (CONN15)
+# ============================================================
+CH0_VNOM="1.5";     CH0_NET="P1V5_AVDD_55"
+CH1_VNOM="0.9";     CH1_NET="P0V9_AVDD_55"
+CH2_VNOM="0.75";    CH2_NET="P0V75_DVDD_63"
+CH3_VNOM="0.75";    CH3_NET="P0V75_AVDD_63"
+CH4_VNOM="1.5";     CH4_NET="P1V5_AVDD_63"
+CH5_VNOM="0.9";     CH5_NET="P0V9_AVDD_63"
+CH6_VNOM="3.3";     CH6_NET="PVDD3_3V_SYNTH_LDO_B3"
+CH7_VNOM="1.5";     CH7_NET="PVDD1V5_3"
+CH8_VNOM="0.85";    CH8_NET="P0V85_STBY"
+CH9_VNOM="1.8";     CH9_NET="P1V8_STBY"
+CH10_VNOM="-";      CH10_NET="NC"
+CH11_VNOM="3.3";    CH11_NET="P3V3_STBY"
+CH12_VNOM="0.9";    CH12_NET="PVDD0V9_2"
+CH13_VNOM="0.75";   CH13_NET="P0V75_DVDD_55"
+CH14_VNOM="0.75";   CH14_NET="P0V75_AVDD_55"
+CH15_VNOM="1.8";    CH15_NET="P1V8_DVDDIO_4"
diff --git a/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN16.conf b/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN16.conf
index 4984a2a..3a05621 100644
--- a/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN16.conf
+++ b/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN16.conf
@@ -1,52 +1,52 @@
-# Blanton Channel Settings
-# Format: CH<n>_VNOM=voltage  CH<n>_NET=net_name
-#
-# Channel numbering (Script Channel, per Blanton_Margin_List):
-#   ch_global / 8 -> CHIPS index (0~17)
-#   ch_global % 8 -> page within LTC2977 (0~7)
-# One LTC2980 = two LTC2977 (8ch each), controlled via 2 I2C addresses.
-
-# --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
-#     it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
-TRANSPORT="swb"
-CB_I2C_CH=8           # CB F3 Ch8 = SWB0 CONN15/CONN16 (shared with CONN15, addr must differ)
-
-# --- I2C Configuration ---
-
-# Format: "bus:address"  (8 channels per entry / per LTC2977)
-CHIPS=(
-    # chip1: SWB0 (CONN16)
-    "0:0x64"    # CH0   ~ CH7
-    "0:0x65"    # CH8   ~ CH15
-)
-
-# Pre-commands to run before accessing each chip (empty = none)
-# Multiple commands separated by ;
-CHIP_PRE_CMD=(
-    ""    # SWB0   CONN16 (lo)
-)
-
-# Post-commands to run after accessing each chip (optional, empty = none)
-CHIP_POST_CMD=(
-    ""    # SWB0   CONN16 (lo)
-)
-
-# ============================================================
-# chip1: SWB0 (CONN16)
-# ============================================================
-CH0_VNOM="1.5";     CH0_NET="PVDD1V5_0"
-CH1_VNOM="1.8";     CH1_NET="P1V8_4"
-CH2_VNOM="3.3";     CH2_NET="PVDD3_3V_SYNTH_LDO_B5"
-CH3_VNOM="3.3";     CH3_NET="PVDD3_3V_SYNTH_LDO_A5"
-CH4_VNOM="3.3";     CH4_NET="PVDD3_3V_SYNTH_LDO_B4"
-CH5_VNOM="3.3";     CH5_NET="PVDD3_3V_SYNTH_LDO_A4"
-CH6_VNOM="3.3";     CH6_NET="P3V3"
-CH7_VNOM="0.8";     CH7_NET="PVDD0_8V_T3"
-CH8_VNOM="0.75";    CH8_NET="P0V75_DVDD_1"
-CH9_VNOM="0.75";    CH9_NET="P0V75_AVDD_1"
-CH10_VNOM="1.5";    CH10_NET="P1V5_AVDD_1"
-CH11_VNOM="0.9";    CH11_NET="P0V9_AVDD_1"
-CH12_VNOM="0.9";    CH12_NET="PVDD0V9_0"
-CH13_VNOM="0.9";    CH13_NET="PVDD0V9_1"
-CH14_VNOM="0.9";    CH14_NET="PVDD0V9_3"
-CH15_VNOM="1.2";    CH15_NET="PVDD1V2_T3"
+# Blanton Channel Settings
+# Format: CH<n>_VNOM=voltage  CH<n>_NET=net_name
+#
+# Channel numbering (Script Channel, per Blanton_Margin_List):
+#   ch_global / 8 -> CHIPS index (0~17)
+#   ch_global % 8 -> page within LTC2977 (0~7)
+# One LTC2980 = two LTC2977 (8ch each), controlled via 2 I2C addresses.
+
+# --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
+#     it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
+TRANSPORT="swb"
+CB_I2C_CH=8           # CB F3 Ch8 = SWB0 CONN15/CONN16 (shared with CONN15, addr must differ)
+
+# --- I2C Configuration ---
+
+# Format: "bus:address"  (8 channels per entry / per LTC2977)
+CHIPS=(
+    # chip1: SWB0 (CONN16)
+    "0:0x64"    # CH0   ~ CH7
+    "0:0x65"    # CH8   ~ CH15
+)
+
+# Pre-commands to run before accessing each chip (empty = none)
+# Multiple commands separated by ;
+CHIP_PRE_CMD=(
+    ""    # SWB0   CONN16 (lo)
+)
+
+# Post-commands to run after accessing each chip (optional, empty = none)
+CHIP_POST_CMD=(
+    ""    # SWB0   CONN16 (lo)
+)
+
+# ============================================================
+# chip1: SWB0 (CONN16)
+# ============================================================
+CH0_VNOM="1.5";     CH0_NET="PVDD1V5_0"
+CH1_VNOM="1.8";     CH1_NET="P1V8_4"
+CH2_VNOM="3.3";     CH2_NET="PVDD3_3V_SYNTH_LDO_B5"
+CH3_VNOM="3.3";     CH3_NET="PVDD3_3V_SYNTH_LDO_A5"
+CH4_VNOM="3.3";     CH4_NET="PVDD3_3V_SYNTH_LDO_B4"
+CH5_VNOM="3.3";     CH5_NET="PVDD3_3V_SYNTH_LDO_A4"
+CH6_VNOM="3.3";     CH6_NET="P3V3"
+CH7_VNOM="0.8";     CH7_NET="PVDD0_8V_T3"
+CH8_VNOM="0.75";    CH8_NET="P0V75_DVDD_1"
+CH9_VNOM="0.75";    CH9_NET="P0V75_AVDD_1"
+CH10_VNOM="1.5";    CH10_NET="P1V5_AVDD_1"
+CH11_VNOM="0.9";    CH11_NET="P0V9_AVDD_1"
+CH12_VNOM="0.9";    CH12_NET="PVDD0V9_0"
+CH13_VNOM="0.9";    CH13_NET="PVDD0V9_1"
+CH14_VNOM="0.9";    CH14_NET="PVDD0V9_3"
+CH15_VNOM="1.2";    CH15_NET="PVDD1V2_T3"
diff --git a/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN13.conf b/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN13.conf
index 355f0c1..742e38f 100644
--- a/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN13.conf
+++ b/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN13.conf
@@ -1,52 +1,52 @@
-# Blanton Channel Settings
-# Format: CH<n>_VNOM=voltage  CH<n>_NET=net_name
-#
-# Channel numbering (Script Channel, per Blanton_Margin_List):
-#   ch_global / 8 -> CHIPS index (0~17)
-#   ch_global % 8 -> page within LTC2977 (0~7)
-# One LTC2980 = two LTC2977 (8ch each), controlled via 2 I2C addresses.
-
-# --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
-#     it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
-TRANSPORT="swb"
-CB_I2C_CH=7           # CB F3 Ch7 = SWB1 CONN13/CONN14 (shared with CONN14, addr must differ)
-
-# --- I2C Configuration ---
-
-# Format: "bus:address"  (8 channels per entry / per LTC2977)
-CHIPS=(
-    # chip1: SWB1 (CONN13)
-    "1:0x5C"    # CH0   ~ CH7
-    "1:0x5D"    # CH8   ~ CH15
-)
-
-# Pre-commands to run before accessing each chip (empty = none)
-# Multiple commands separated by ;
-CHIP_PRE_CMD=(
-    ""    # SWB1   CONN13 (lo)
-)
-
-# Post-commands to run after accessing each chip (optional, empty = none)
-CHIP_POST_CMD=(
-    ""    # SWB1   CONN13 (lo)
-)
-
-# ============================================================
-# chip1: SWB1 (CONN13)
-# ============================================================
-CH0_VNOM="0.75";    CH0_NET="P0V75_DVDD_47"
-CH1_VNOM="0.75";    CH1_NET="P0V75_AVDD_47"
-CH2_VNOM="1.5";     CH2_NET="P1V5_AVDD_47"
-CH3_VNOM="0.9";     CH3_NET="P0V9_AVDD_47"
-CH4_VNOM="1.8";     CH4_NET="P1V8_1"
-CH5_VNOM="3.3";     CH5_NET="PVDD3_3V_SYNTH_LDO_A3"
-CH6_VNOM="3.3";     CH6_NET="PVDD3_3V_SYNTH_LDO_B1"
-CH7_VNOM="1.8";     CH7_NET="P1V8_3"
-CH8_VNOM="1.8";     CH8_NET="P1V8_DVDDIO_3"
-CH9_VNOM="0.75";    CH9_NET="P0V75_DVDD_39"
-CH10_VNOM="0.75";   CH10_NET="P0V75_AVDD_39"
-CH11_VNOM="1.5";    CH11_NET="P1V5_AVDD_39"
-CH12_VNOM="0.9";    CH12_NET="P0V9_AVDD_39"
-CH13_VNOM="1.5";    CH13_NET="PVDD1V5_2"
-CH14_VNOM="1.8";    CH14_NET="PVDD1V8_DUT"
-CH15_VNOM="1.2";    CH15_NET="PVDD_MDIO"
+# Blanton Channel Settings
+# Format: CH<n>_VNOM=voltage  CH<n>_NET=net_name
+#
+# Channel numbering (Script Channel, per Blanton_Margin_List):
+#   ch_global / 8 -> CHIPS index (0~17)
+#   ch_global % 8 -> page within LTC2977 (0~7)
+# One LTC2980 = two LTC2977 (8ch each), controlled via 2 I2C addresses.
+
+# --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
+#     it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
+TRANSPORT="swb"
+CB_I2C_CH=7           # CB F3 Ch7 = SWB1 CONN13/CONN14 (shared with CONN14, addr must differ)
+
+# --- I2C Configuration ---
+
+# Format: "bus:address"  (8 channels per entry / per LTC2977)
+CHIPS=(
+    # chip1: SWB1 (CONN13)
+    "1:0x5C"    # CH0   ~ CH7
+    "1:0x5D"    # CH8   ~ CH15
+)
+
+# Pre-commands to run before accessing each chip (empty = none)
+# Multiple commands separated by ;
+CHIP_PRE_CMD=(
+    ""    # SWB1   CONN13 (lo)
+)
+
+# Post-commands to run after accessing each chip (optional, empty = none)
+CHIP_POST_CMD=(
+    ""    # SWB1   CONN13 (lo)
+)
+
+# ============================================================
+# chip1: SWB1 (CONN13)
+# ============================================================
+CH0_VNOM="0.75";    CH0_NET="P0V75_DVDD_47"
+CH1_VNOM="0.75";    CH1_NET="P0V75_AVDD_47"
+CH2_VNOM="1.5";     CH2_NET="P1V5_AVDD_47"
+CH3_VNOM="0.9";     CH3_NET="P0V9_AVDD_47"
+CH4_VNOM="1.8";     CH4_NET="P1V8_1"
+CH5_VNOM="3.3";     CH5_NET="PVDD3_3V_SYNTH_LDO_A3"
+CH6_VNOM="3.3";     CH6_NET="PVDD3_3V_SYNTH_LDO_B1"
+CH7_VNOM="1.8";     CH7_NET="P1V8_3"
+CH8_VNOM="1.8";     CH8_NET="P1V8_DVDDIO_3"
+CH9_VNOM="0.75";    CH9_NET="P0V75_DVDD_39"
+CH10_VNOM="0.75";   CH10_NET="P0V75_AVDD_39"
+CH11_VNOM="1.5";    CH11_NET="P1V5_AVDD_39"
+CH12_VNOM="0.9";    CH12_NET="P0V9_AVDD_39"
+CH13_VNOM="1.5";    CH13_NET="PVDD1V5_2"
+CH14_VNOM="1.8";    CH14_NET="PVDD1V8_DUT"
+CH15_VNOM="1.2";    CH15_NET="PVDD_MDIO"
diff --git a/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN14.conf b/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN14.conf
index ce2efe5..e2efc1a 100644
--- a/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN14.conf
+++ b/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN14.conf
@@ -1,52 +1,52 @@
-# Blanton Channel Settings
-# Format: CH<n>_VNOM=voltage  CH<n>_NET=net_name
-#
-# Channel numbering (Script Channel, per Blanton_Margin_List):
-#   ch_global / 8 -> CHIPS index (0~17)
-#   ch_global % 8 -> page within LTC2977 (0~7)
-# One LTC2980 = two LTC2977 (8ch each), controlled via 2 I2C addresses.
-
-# --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
-#     it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
-TRANSPORT="swb"
-CB_I2C_CH=7           # CB F3 Ch7 = SWB1 CONN13/CONN14 (shared with CONN13, addr must differ)
-
-# --- I2C Configuration ---
-
-# Format: "bus:address"  (8 channels per entry / per LTC2977)
-CHIPS=(
-    # chip1: SWB1 (CONN14)
-    "1:0x5E"    # CH0   ~ CH7
-    "1:0x5F"    # CH8   ~ CH15
-)
-
-# Pre-commands to run before accessing each chip (empty = none)
-# Multiple commands separated by ;
-CHIP_PRE_CMD=(
-    ""    # SWB1   CONN14 (lo)
-)
-
-# Post-commands to run after accessing each chip (optional, empty = none)
-CHIP_POST_CMD=(
-    ""    # SWB1   CONN14 (lo)
-)
-
-# ============================================================
-# chip1: SWB1 (CONN14)
-# ============================================================
-CH0_VNOM="0.75";    CH0_NET="P0V75_AVDD_7"
-CH1_VNOM="1.5";     CH1_NET="P1V5_AVDD_7"
-CH2_VNOM="0.9";     CH2_NET="P0V9_AVDD_7"
-CH3_VNOM="1.8";     CH3_NET="P1V8_5"
-CH4_VNOM="1.8";     CH4_NET="P1V8_2"
-CH5_VNOM="3.3";     CH5_NET="PVDD3_3V_SYNTH_LDO_B2"
-CH6_VNOM="3.3";     CH6_NET="PVDD3_3V_SYNTH_LDO_A2"
-CH7_VNOM="3.3";     CH7_NET="PVDD3_3V_SYNTH_LDO_A1"
-CH8_VNOM="1.5";     CH8_NET="PVDD1V5_TSC"
-CH9_VNOM="1.5";     CH9_NET="PVDD1V5_ANLG"
-CH10_VNOM="-";      CH10_NET="NC"
-CH11_VNOM="-";      CH11_NET="NC"
-CH12_VNOM="1.5";    CH12_NET="PVDD1V5_1"
-CH13_VNOM="-";      CH13_NET="NC"
-CH14_VNOM="1.8";    CH14_NET="P1V8_DVDDIO_1"
-CH15_VNOM="0.75";   CH15_NET="P0V75_DVDD_7"
+# Blanton Channel Settings
+# Format: CH<n>_VNOM=voltage  CH<n>_NET=net_name
+#
+# Channel numbering (Script Channel, per Blanton_Margin_List):
+#   ch_global / 8 -> CHIPS index (0~17)
+#   ch_global % 8 -> page within LTC2977 (0~7)
+# One LTC2980 = two LTC2977 (8ch each), controlled via 2 I2C addresses.
+
+# --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
+#     it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
+TRANSPORT="swb"
+CB_I2C_CH=7           # CB F3 Ch7 = SWB1 CONN13/CONN14 (shared with CONN13, addr must differ)
+
+# --- I2C Configuration ---
+
+# Format: "bus:address"  (8 channels per entry / per LTC2977)
+CHIPS=(
+    # chip1: SWB1 (CONN14)
+    "1:0x5E"    # CH0   ~ CH7
+    "1:0x5F"    # CH8   ~ CH15
+)
+
+# Pre-commands to run before accessing each chip (empty = none)
+# Multiple commands separated by ;
+CHIP_PRE_CMD=(
+    ""    # SWB1   CONN14 (lo)
+)
+
+# Post-commands to run after accessing each chip (optional, empty = none)
+CHIP_POST_CMD=(
+    ""    # SWB1   CONN14 (lo)
+)
+
+# ============================================================
+# chip1: SWB1 (CONN14)
+# ============================================================
+CH0_VNOM="0.75";    CH0_NET="P0V75_AVDD_7"
+CH1_VNOM="1.5";     CH1_NET="P1V5_AVDD_7"
+CH2_VNOM="0.9";     CH2_NET="P0V9_AVDD_7"
+CH3_VNOM="1.8";     CH3_NET="P1V8_5"
+CH4_VNOM="1.8";     CH4_NET="P1V8_2"
+CH5_VNOM="3.3";     CH5_NET="PVDD3_3V_SYNTH_LDO_B2"
+CH6_VNOM="3.3";     CH6_NET="PVDD3_3V_SYNTH_LDO_A2"
+CH7_VNOM="3.3";     CH7_NET="PVDD3_3V_SYNTH_LDO_A1"
+CH8_VNOM="1.5";     CH8_NET="PVDD1V5_TSC"
+CH9_VNOM="1.5";     CH9_NET="PVDD1V5_ANLG"
+CH10_VNOM="-";      CH10_NET="NC"
+CH11_VNOM="-";      CH11_NET="NC"
+CH12_VNOM="1.5";    CH12_NET="PVDD1V5_1"
+CH13_VNOM="-";      CH13_NET="NC"
+CH14_VNOM="1.8";    CH14_NET="P1V8_DVDDIO_1"
+CH15_VNOM="0.75";   CH15_NET="P0V75_DVDD_7"
diff --git a/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN15.conf b/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN15.conf
index c99677b..d341e4a 100644
--- a/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN15.conf
+++ b/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN15.conf
@@ -1,52 +1,52 @@
-# Blanton Channel Settings
-# Format: CH<n>_VNOM=voltage  CH<n>_NET=net_name
-#
-# Channel numbering (Script Channel, per Blanton_Margin_List):
-#   ch_global / 8 -> CHIPS index (0~17)
-#   ch_global % 8 -> page within LTC2977 (0~7)
-# One LTC2980 = two LTC2977 (8ch each), controlled via 2 I2C addresses.
-
-# --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
-#     it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
-TRANSPORT="swb"
-CB_I2C_CH=9           # CB F3 Ch9 = SWB1 CONN15/CONN16 (shared with CONN16, addr must differ)
-
-# --- I2C Configuration ---
-
-# Format: "bus:address"  (8 channels per entry / per LTC2977)
-CHIPS=(
-    # chip1: SWB1 (CONN15)
-    "1:0x62"    # CH0   ~ CH7
-    "1:0x63"    # CH8   ~ CH15
-)
-
-# Pre-commands to run before accessing each chip (empty = none)
-# Multiple commands separated by ;
-CHIP_PRE_CMD=(
-    ""    # SWB1   CONN15 (lo)
-)
-
-# Post-commands to run after accessing each chip (optional, empty = none)
-CHIP_POST_CMD=(
-    ""    # SWB1   CONN15 (lo)
-)
-
-# ============================================================
-# chip1: SWB1 (CONN15)
-# ============================================================
-CH0_VNOM="1.5";     CH0_NET="P1V5_AVDD_55"
-CH1_VNOM="0.9";     CH1_NET="P0V9_AVDD_55"
-CH2_VNOM="0.75";    CH2_NET="P0V75_DVDD_63"
-CH3_VNOM="0.75";    CH3_NET="P0V75_AVDD_63"
-CH4_VNOM="1.5";     CH4_NET="P1V5_AVDD_63"
-CH5_VNOM="0.9";     CH5_NET="P0V9_AVDD_63"
-CH6_VNOM="3.3";     CH6_NET="PVDD3_3V_SYNTH_LDO_B3"
-CH7_VNOM="1.5";     CH7_NET="PVDD1V5_3"
-CH8_VNOM="0.85";    CH8_NET="P0V85_STBY"
-CH9_VNOM="1.8";     CH9_NET="P1V8_STBY"
-CH10_VNOM="-";      CH10_NET="NC"
-CH11_VNOM="3.3";    CH11_NET="P3V3_STBY"
-CH12_VNOM="0.9";    CH12_NET="PVDD0V9_2"
-CH13_VNOM="0.75";   CH13_NET="P0V75_DVDD_55"
-CH14_VNOM="0.75";   CH14_NET="P0V75_AVDD_55"
-CH15_VNOM="1.8";    CH15_NET="P1V8_DVDDIO_4"
+# Blanton Channel Settings
+# Format: CH<n>_VNOM=voltage  CH<n>_NET=net_name
+#
+# Channel numbering (Script Channel, per Blanton_Margin_List):
+#   ch_global / 8 -> CHIPS index (0~17)
+#   ch_global % 8 -> page within LTC2977 (0~7)
+# One LTC2980 = two LTC2977 (8ch each), controlled via 2 I2C addresses.
+
+# --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
+#     it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
+TRANSPORT="swb"
+CB_I2C_CH=9           # CB F3 Ch9 = SWB1 CONN15/CONN16 (shared with CONN16, addr must differ)
+
+# --- I2C Configuration ---
+
+# Format: "bus:address"  (8 channels per entry / per LTC2977)
+CHIPS=(
+    # chip1: SWB1 (CONN15)
+    "1:0x62"    # CH0   ~ CH7
+    "1:0x63"    # CH8   ~ CH15
+)
+
+# Pre-commands to run before accessing each chip (empty = none)
+# Multiple commands separated by ;
+CHIP_PRE_CMD=(
+    ""    # SWB1   CONN15 (lo)
+)
+
+# Post-commands to run after accessing each chip (optional, empty = none)
+CHIP_POST_CMD=(
+    ""    # SWB1   CONN15 (lo)
+)
+
+# ============================================================
+# chip1: SWB1 (CONN15)
+# ============================================================
+CH0_VNOM="1.5";     CH0_NET="P1V5_AVDD_55"
+CH1_VNOM="0.9";     CH1_NET="P0V9_AVDD_55"
+CH2_VNOM="0.75";    CH2_NET="P0V75_DVDD_63"
+CH3_VNOM="0.75";    CH3_NET="P0V75_AVDD_63"
+CH4_VNOM="1.5";     CH4_NET="P1V5_AVDD_63"
+CH5_VNOM="0.9";     CH5_NET="P0V9_AVDD_63"
+CH6_VNOM="3.3";     CH6_NET="PVDD3_3V_SYNTH_LDO_B3"
+CH7_VNOM="1.5";     CH7_NET="PVDD1V5_3"
+CH8_VNOM="0.85";    CH8_NET="P0V85_STBY"
+CH9_VNOM="1.8";     CH9_NET="P1V8_STBY"
+CH10_VNOM="-";      CH10_NET="NC"
+CH11_VNOM="3.3";    CH11_NET="P3V3_STBY"
+CH12_VNOM="0.9";    CH12_NET="PVDD0V9_2"
+CH13_VNOM="0.75";   CH13_NET="P0V75_DVDD_55"
+CH14_VNOM="0.75";   CH14_NET="P0V75_AVDD_55"
+CH15_VNOM="1.8";    CH15_NET="P1V8_DVDDIO_4"
diff --git a/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN16.conf b/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN16.conf
index 6159181..5f4bd2a 100644
--- a/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN16.conf
+++ b/src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN16.conf
@@ -1,52 +1,52 @@
-# Blanton Channel Settings
-# Format: CH<n>_VNOM=voltage  CH<n>_NET=net_name
-#
-# Channel numbering (Script Channel, per Blanton_Margin_List):
-#   ch_global / 8 -> CHIPS index (0~17)
-#   ch_global % 8 -> page within LTC2977 (0~7)
-# One LTC2980 = two LTC2977 (8ch each), controlled via 2 I2C addresses.
-
-# --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
-#     it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
-TRANSPORT="swb"
-CB_I2C_CH=9           # CB F3 Ch9 = SWB1 CONN15/CONN16 (shared with CONN15, addr must differ)
-
-# --- I2C Configuration ---
-
-# Format: "bus:address"  (8 channels per entry / per LTC2977)
-CHIPS=(
-    # chip1: SWB1 (CONN16)
-    "1:0x64"    # CH0   ~ CH7
-    "1:0x65"    # CH8   ~ CH15
-)
-
-# Pre-commands to run before accessing each chip (empty = none)
-# Multiple commands separated by ;
-CHIP_PRE_CMD=(
-    ""    # SWB1   CONN16 (lo)
-)
-
-# Post-commands to run after accessing each chip (optional, empty = none)
-CHIP_POST_CMD=(
-    ""    # SWB1   CONN16 (lo)
-)
-
-# ============================================================
-# chip1: SWB1 (CONN16)
-# ============================================================
-CH0_VNOM="1.5";     CH0_NET="PVDD1V5_0"
-CH1_VNOM="1.8";     CH1_NET="P1V8_4"
-CH2_VNOM="3.3";     CH2_NET="PVDD3_3V_SYNTH_LDO_B5"
-CH3_VNOM="3.3";     CH3_NET="PVDD3_3V_SYNTH_LDO_A5"
-CH4_VNOM="3.3";     CH4_NET="PVDD3_3V_SYNTH_LDO_B4"
-CH5_VNOM="3.3";     CH5_NET="PVDD3_3V_SYNTH_LDO_A4"
-CH6_VNOM="3.3";     CH6_NET="P3V3"
-CH7_VNOM="0.8";     CH7_NET="PVDD0_8V_T3"
-CH8_VNOM="0.75";    CH8_NET="P0V75_DVDD_1"
-CH9_VNOM="0.75";    CH9_NET="P0V75_AVDD_1"
-CH10_VNOM="1.5";    CH10_NET="P1V5_AVDD_1"
-CH11_VNOM="0.9";    CH11_NET="P0V9_AVDD_1"
-CH12_VNOM="0.9";    CH12_NET="PVDD0V9_0"
-CH13_VNOM="0.9";    CH13_NET="PVDD0V9_1"
-CH14_VNOM="0.9";    CH14_NET="PVDD0V9_3"
-CH15_VNOM="1.2";    CH15_NET="PVDD1V2_T3"
+# Blanton Channel Settings
+# Format: CH<n>_VNOM=voltage  CH<n>_NET=net_name
+#
+# Channel numbering (Script Channel, per Blanton_Margin_List):
+#   ch_global / 8 -> CHIPS index (0~17)
+#   ch_global % 8 -> page within LTC2977 (0~7)
+# One LTC2980 = two LTC2977 (8ch each), controlled via 2 I2C addresses.
+
+# --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
+#     it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
+TRANSPORT="swb"
+CB_I2C_CH=9           # CB F3 Ch9 = SWB1 CONN15/CONN16 (shared with CONN15, addr must differ)
+
+# --- I2C Configuration ---
+
+# Format: "bus:address"  (8 channels per entry / per LTC2977)
+CHIPS=(
+    # chip1: SWB1 (CONN16)
+    "1:0x64"    # CH0   ~ CH7
+    "1:0x65"    # CH8   ~ CH15
+)
+
+# Pre-commands to run before accessing each chip (empty = none)
+# Multiple commands separated by ;
+CHIP_PRE_CMD=(
+    ""    # SWB1   CONN16 (lo)
+)
+
+# Post-commands to run after accessing each chip (optional, empty = none)
+CHIP_POST_CMD=(
+    ""    # SWB1   CONN16 (lo)
+)
+
+# ============================================================
+# chip1: SWB1 (CONN16)
+# ============================================================
+CH0_VNOM="1.5";     CH0_NET="PVDD1V5_0"
+CH1_VNOM="1.8";     CH1_NET="P1V8_4"
+CH2_VNOM="3.3";     CH2_NET="PVDD3_3V_SYNTH_LDO_B5"
+CH3_VNOM="3.3";     CH3_NET="PVDD3_3V_SYNTH_LDO_A5"
+CH4_VNOM="3.3";     CH4_NET="PVDD3_3V_SYNTH_LDO_B4"
+CH5_VNOM="3.3";     CH5_NET="PVDD3_3V_SYNTH_LDO_A4"
+CH6_VNOM="3.3";     CH6_NET="P3V3"
+CH7_VNOM="0.8";     CH7_NET="PVDD0_8V_T3"
+CH8_VNOM="0.75";    CH8_NET="P0V75_DVDD_1"
+CH9_VNOM="0.75";    CH9_NET="P0V75_AVDD_1"
+CH10_VNOM="1.5";    CH10_NET="P1V5_AVDD_1"
+CH11_VNOM="0.9";    CH11_NET="P0V9_AVDD_1"
+CH12_VNOM="0.9";    CH12_NET="PVDD0V9_0"
+CH13_VNOM="0.9";    CH13_NET="PVDD0V9_1"
+CH14_VNOM="0.9";    CH14_NET="PVDD0V9_3"
+CH15_VNOM="1.2";    CH15_NET="PVDD1V2_T3"