fix(margin): Convert margin.sh and settings to LF, pin line endings
margin.sh and settings/*.conf carried CRLF into the repo, so sourcing
them on the SONiC DUT failed outright:
-bash: $'\r': command not found
margin.sh: line 126: syntax error near unexpected token `$'{\r''
settings/*.conf was the quieter half of the same bug: margin_init
sources them, and an unquoted assignment such as CB_I2C_CH=6 became
"6\r", so the SWB transport would have driven I2C with a malformed
channel number.
Content is unchanged - the diff is carriage returns only, and bash -n
passes on every converted file.
Add .gitattributes so this cannot come back: *.sh/*.conf/*.py/*.txt/*.md
are pinned to LF, *.ttl stays CRLF (Tera Term runs on Windows only) and
office formats are marked binary.
Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_014RetWKFZFG1ZHcitQAyhwM
This commit is contained in:
Claude Opus 5
@@ -0,0 +1,29 @@
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|||||||
|
# =============================================================================
|
||||||
|
# 換行符政策
|
||||||
|
# -----------------------------------------------------------------------------
|
||||||
|
# 這個 repo 同時被 Windows（Tera Term 端編輯）與 SONiC/Linux（DUT 端執行）使用，
|
||||||
|
# 所以必須明確指定，不能靠各機器的 core.autocrlf。
|
||||||
|
#
|
||||||
|
# 踩過的坑：margin.sh 帶著 CRLF 進 repo，scp 到 DUT 後 bash 直接掛：
|
||||||
|
# -bash: $'\r': command not found
|
||||||
|
# syntax error near unexpected token `$'{\r''
|
||||||
|
# settings/*.conf 同樣危險 —— margin_init 是用 source 讀它們的，未加引號的
|
||||||
|
# 賦值（例如 CB_I2C_CH=6）會變成 "6\r"，SWB transport 會拿著壞掉的通道號去打 I2C。
|
||||||
|
# =============================================================================
|
||||||
|
|
||||||
|
# 在 DUT / Linux 上執行或被 source 的，一律 LF
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||||||
|
*.sh text eol=lf
|
||||||
|
*.conf text eol=lf
|
||||||
|
*.py text eol=lf
|
||||||
|
*.txt text eol=lf
|
||||||
|
*.md text eol=lf
|
||||||
|
|
||||||
|
# Tera Term macro 只在 Windows 上跑，維持 CRLF；標成 -text 讓 git 原樣保存，
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||||||
|
# 避免對既有檔案產生大量純換行符的假 diff
|
||||||
|
*.ttl -text
|
||||||
|
|
||||||
|
# 二進位，不要做任何轉換
|
||||||
|
*.xlsx binary
|
||||||
|
*.docx binary
|
||||||
|
*.pdf binary
|
||||||
|
*.h5 binary
|
||||||
File diff suppressed because it is too large
Load Diff
+52
-52
@@ -1,52 +1,52 @@
|
|||||||
# Blanton Channel Settings
|
# Blanton Channel Settings
|
||||||
# Format: CH<n>_VNOM=voltage CH<n>_NET=net_name
|
# Format: CH<n>_VNOM=voltage CH<n>_NET=net_name
|
||||||
#
|
#
|
||||||
# Channel numbering (Script Channel, per Blanton_Margin_List):
|
# Channel numbering (Script Channel, per Blanton_Margin_List):
|
||||||
# ch_global / 8 -> CHIPS index (0~17)
|
# ch_global / 8 -> CHIPS index (0~17)
|
||||||
# ch_global % 8 -> page within LTC2977 (0~7)
|
# ch_global % 8 -> page within LTC2977 (0~7)
|
||||||
# One LTC2980 = two LTC2977 (8ch each), controlled via 2 I2C addresses.
|
# One LTC2980 = two LTC2977 (8ch each), controlled via 2 I2C addresses.
|
||||||
|
|
||||||
# --- Transport (blank = i2c): CB's LTC2980 is on the native I2C bus, driven by
|
# --- Transport (blank = i2c): CB's LTC2980 is on the native I2C bus, driven by
|
||||||
# i2cset/i2cget. Only SWB boards set TRANSPORT="swb" + CB_I2C_CH=<6|7|8|9>. ---
|
# i2cset/i2cget. Only SWB boards set TRANSPORT="swb" + CB_I2C_CH=<6|7|8|9>. ---
|
||||||
TRANSPORT=""
|
TRANSPORT=""
|
||||||
CB_I2C_CH=
|
CB_I2C_CH=
|
||||||
|
|
||||||
# --- I2C Configuration ---
|
# --- I2C Configuration ---
|
||||||
|
|
||||||
# Format: "bus:address" (8 channels per entry / per LTC2977)
|
# Format: "bus:address" (8 channels per entry / per LTC2977)
|
||||||
CHIPS=(
|
CHIPS=(
|
||||||
# chip1: CB (CONN13)
|
# chip1: CB (CONN13)
|
||||||
"4:0x5C" # CH0 ~ CH7
|
"4:0x5C" # CH0 ~ CH7
|
||||||
"4:0x5E" # CH8 ~ CH15
|
"4:0x5E" # CH8 ~ CH15
|
||||||
)
|
)
|
||||||
|
|
||||||
# Pre-commands to run before accessing each chip (empty = none)
|
# Pre-commands to run before accessing each chip (empty = none)
|
||||||
# Multiple commands separated by ;
|
# Multiple commands separated by ;
|
||||||
CHIP_PRE_CMD=(
|
CHIP_PRE_CMD=(
|
||||||
"" # CB CONN13 (lo)
|
"" # CB CONN13 (lo)
|
||||||
)
|
)
|
||||||
|
|
||||||
# Post-commands to run after accessing each chip (optional, empty = none)
|
# Post-commands to run after accessing each chip (optional, empty = none)
|
||||||
CHIP_POST_CMD=(
|
CHIP_POST_CMD=(
|
||||||
"" # CB CONN13 (lo)
|
"" # CB CONN13 (lo)
|
||||||
)
|
)
|
||||||
|
|
||||||
# ============================================================
|
# ============================================================
|
||||||
# chip1: CB (CONN13)
|
# chip1: CB (CONN13)
|
||||||
# ============================================================
|
# ============================================================
|
||||||
CH0_VNOM="5.0"; CH0_NET="V5P0_ALW"
|
CH0_VNOM="5.0"; CH0_NET="V5P0_ALW"
|
||||||
CH1_VNOM="3.3"; CH1_NET="V3P3_ALW"
|
CH1_VNOM="3.3"; CH1_NET="V3P3_ALW"
|
||||||
CH2_VNOM="0.75"; CH2_NET="PWR_VDD_MISC_ALW"
|
CH2_VNOM="0.75"; CH2_NET="PWR_VDD_MISC_ALW"
|
||||||
CH3_VNOM="1.8"; CH3_NET="V1P8_ALW"
|
CH3_VNOM="1.8"; CH3_NET="V1P8_ALW"
|
||||||
CH4_VNOM="1.1"; CH4_NET="PWR_APU_VDDIO_SUS"
|
CH4_VNOM="1.1"; CH4_NET="PWR_APU_VDDIO_SUS"
|
||||||
CH5_VNOM="0.75"; CH5_NET="PWR_VDD_MISC_RUN"
|
CH5_VNOM="0.75"; CH5_NET="PWR_VDD_MISC_RUN"
|
||||||
CH6_VNOM="0.78"; CH6_NET="PWR_APU_VDD_MEM_RUN"
|
CH6_VNOM="0.78"; CH6_NET="PWR_APU_VDD_MEM_RUN"
|
||||||
CH7_VNOM="0.8"; CH7_NET="V0P8_PHY2_DVDD"
|
CH7_VNOM="0.8"; CH7_NET="V0P8_PHY2_DVDD"
|
||||||
CH8_VNOM="0.8"; CH8_NET="V0P8_AVDD"
|
CH8_VNOM="0.8"; CH8_NET="V0P8_AVDD"
|
||||||
CH9_VNOM="0.8"; CH9_NET="V0P8_PHY"
|
CH9_VNOM="0.8"; CH9_NET="V0P8_PHY"
|
||||||
CH10_VNOM="1.8"; CH10_NET="V1P8_FPGA"
|
CH10_VNOM="1.8"; CH10_NET="V1P8_FPGA"
|
||||||
CH11_VNOM="2.5"; CH11_NET="V2P5_FPGA"
|
CH11_VNOM="2.5"; CH11_NET="V2P5_FPGA"
|
||||||
CH12_VNOM="1.1"; CH12_NET="V1P1_FPGA"
|
CH12_VNOM="1.1"; CH12_NET="V1P1_FPGA"
|
||||||
CH13_VNOM="5.0"; CH13_NET="P5V_STBY"
|
CH13_VNOM="5.0"; CH13_NET="P5V_STBY"
|
||||||
CH14_VNOM="3.3"; CH14_NET="P3V3_STBY"
|
CH14_VNOM="3.3"; CH14_NET="P3V3_STBY"
|
||||||
CH15_VNOM="0.8"; CH15_NET="V0P8_PHY2_AVDD"
|
CH15_VNOM="0.8"; CH15_NET="V0P8_PHY2_AVDD"
|
||||||
|
|||||||
+52
-52
@@ -1,52 +1,52 @@
|
|||||||
# Blanton Channel Settings
|
# Blanton Channel Settings
|
||||||
# Format: CH<n>_VNOM=voltage CH<n>_NET=net_name
|
# Format: CH<n>_VNOM=voltage CH<n>_NET=net_name
|
||||||
#
|
#
|
||||||
# Channel numbering (Script Channel, per Blanton_Margin_List):
|
# Channel numbering (Script Channel, per Blanton_Margin_List):
|
||||||
# ch_global / 8 -> CHIPS index (0~17)
|
# ch_global / 8 -> CHIPS index (0~17)
|
||||||
# ch_global % 8 -> page within LTC2977 (0~7)
|
# ch_global % 8 -> page within LTC2977 (0~7)
|
||||||
# One LTC2980 = two LTC2977 (8ch each), controlled via 2 I2C addresses.
|
# One LTC2980 = two LTC2977 (8ch each), controlled via 2 I2C addresses.
|
||||||
|
|
||||||
# --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
|
# --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
|
||||||
# it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
|
# it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
|
||||||
TRANSPORT="swb"
|
TRANSPORT="swb"
|
||||||
CB_I2C_CH=6 # CB F3 Ch6 = SWB0 CONN13/CONN14 (shared with CONN14, addr must differ)
|
CB_I2C_CH=6 # CB F3 Ch6 = SWB0 CONN13/CONN14 (shared with CONN14, addr must differ)
|
||||||
|
|
||||||
# --- I2C Configuration ---
|
# --- I2C Configuration ---
|
||||||
|
|
||||||
# Format: "bus:address" (8 channels per entry / per LTC2977)
|
# Format: "bus:address" (8 channels per entry / per LTC2977)
|
||||||
CHIPS=(
|
CHIPS=(
|
||||||
# chip1: SWB0 (CONN13)
|
# chip1: SWB0 (CONN13)
|
||||||
"0:0x5C" # CH0 ~ CH7
|
"0:0x5C" # CH0 ~ CH7
|
||||||
"0:0x5E" # CH8 ~ CH15
|
"0:0x5E" # CH8 ~ CH15
|
||||||
)
|
)
|
||||||
|
|
||||||
# Pre-commands to run before accessing each chip (empty = none)
|
# Pre-commands to run before accessing each chip (empty = none)
|
||||||
# Multiple commands separated by ;
|
# Multiple commands separated by ;
|
||||||
CHIP_PRE_CMD=(
|
CHIP_PRE_CMD=(
|
||||||
"" # SWB0 CONN13 (lo)
|
"" # SWB0 CONN13 (lo)
|
||||||
)
|
)
|
||||||
|
|
||||||
# Post-commands to run after accessing each chip (optional, empty = none)
|
# Post-commands to run after accessing each chip (optional, empty = none)
|
||||||
CHIP_POST_CMD=(
|
CHIP_POST_CMD=(
|
||||||
"" # SWB0 CONN13 (lo)
|
"" # SWB0 CONN13 (lo)
|
||||||
)
|
)
|
||||||
|
|
||||||
# ============================================================
|
# ============================================================
|
||||||
# chip1: SWB0 (CONN13)
|
# chip1: SWB0 (CONN13)
|
||||||
# ============================================================
|
# ============================================================
|
||||||
CH0_VNOM="0.75"; CH0_NET="P0V75_DVDD_47"
|
CH0_VNOM="0.75"; CH0_NET="P0V75_DVDD_47"
|
||||||
CH1_VNOM="0.75"; CH1_NET="P0V75_AVDD_47"
|
CH1_VNOM="0.75"; CH1_NET="P0V75_AVDD_47"
|
||||||
CH2_VNOM="1.5"; CH2_NET="P1V5_AVDD_47"
|
CH2_VNOM="1.5"; CH2_NET="P1V5_AVDD_47"
|
||||||
CH3_VNOM="0.9"; CH3_NET="P0V9_AVDD_47"
|
CH3_VNOM="0.9"; CH3_NET="P0V9_AVDD_47"
|
||||||
CH4_VNOM="1.8"; CH4_NET="P1V8_1"
|
CH4_VNOM="1.8"; CH4_NET="P1V8_1"
|
||||||
CH5_VNOM="3.3"; CH5_NET="PVDD3_3V_SYNTH_LDO_A3"
|
CH5_VNOM="3.3"; CH5_NET="PVDD3_3V_SYNTH_LDO_A3"
|
||||||
CH6_VNOM="3.3"; CH6_NET="PVDD3_3V_SYNTH_LDO_B1"
|
CH6_VNOM="3.3"; CH6_NET="PVDD3_3V_SYNTH_LDO_B1"
|
||||||
CH7_VNOM="1.8"; CH7_NET="P1V8_3"
|
CH7_VNOM="1.8"; CH7_NET="P1V8_3"
|
||||||
CH8_VNOM="1.8"; CH8_NET="P1V8_DVDDIO_3"
|
CH8_VNOM="1.8"; CH8_NET="P1V8_DVDDIO_3"
|
||||||
CH9_VNOM="0.75"; CH9_NET="P0V75_DVDD_39"
|
CH9_VNOM="0.75"; CH9_NET="P0V75_DVDD_39"
|
||||||
CH10_VNOM="0.75"; CH10_NET="P0V75_AVDD_39"
|
CH10_VNOM="0.75"; CH10_NET="P0V75_AVDD_39"
|
||||||
CH11_VNOM="1.5"; CH11_NET="P1V5_AVDD_39"
|
CH11_VNOM="1.5"; CH11_NET="P1V5_AVDD_39"
|
||||||
CH12_VNOM="0.9"; CH12_NET="P0V9_AVDD_39"
|
CH12_VNOM="0.9"; CH12_NET="P0V9_AVDD_39"
|
||||||
CH13_VNOM="1.5"; CH13_NET="PVDD1V5_2"
|
CH13_VNOM="1.5"; CH13_NET="PVDD1V5_2"
|
||||||
CH14_VNOM="1.8"; CH14_NET="PVDD1V8_DUT"
|
CH14_VNOM="1.8"; CH14_NET="PVDD1V8_DUT"
|
||||||
CH15_VNOM="1.2"; CH15_NET="PVDD_MDIO"
|
CH15_VNOM="1.2"; CH15_NET="PVDD_MDIO"
|
||||||
|
|||||||
+52
-52
@@ -1,52 +1,52 @@
|
|||||||
# Blanton Channel Settings
|
# Blanton Channel Settings
|
||||||
# Format: CH<n>_VNOM=voltage CH<n>_NET=net_name
|
# Format: CH<n>_VNOM=voltage CH<n>_NET=net_name
|
||||||
#
|
#
|
||||||
# Channel numbering (Script Channel, per Blanton_Margin_List):
|
# Channel numbering (Script Channel, per Blanton_Margin_List):
|
||||||
# ch_global / 8 -> CHIPS index (0~17)
|
# ch_global / 8 -> CHIPS index (0~17)
|
||||||
# ch_global % 8 -> page within LTC2977 (0~7)
|
# ch_global % 8 -> page within LTC2977 (0~7)
|
||||||
# One LTC2980 = two LTC2977 (8ch each), controlled via 2 I2C addresses.
|
# One LTC2980 = two LTC2977 (8ch each), controlled via 2 I2C addresses.
|
||||||
|
|
||||||
# --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
|
# --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
|
||||||
# it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
|
# it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
|
||||||
TRANSPORT="swb"
|
TRANSPORT="swb"
|
||||||
CB_I2C_CH=6 # CB F3 Ch6 = SWB0 CONN13/CONN14 (shared with CONN13, addr must differ)
|
CB_I2C_CH=6 # CB F3 Ch6 = SWB0 CONN13/CONN14 (shared with CONN13, addr must differ)
|
||||||
|
|
||||||
# --- I2C Configuration ---
|
# --- I2C Configuration ---
|
||||||
|
|
||||||
# Format: "bus:address" (8 channels per entry / per LTC2977)
|
# Format: "bus:address" (8 channels per entry / per LTC2977)
|
||||||
CHIPS=(
|
CHIPS=(
|
||||||
# chip1: SWB0 (CONN14)
|
# chip1: SWB0 (CONN14)
|
||||||
"0:0x5E" # CH0 ~ CH7
|
"0:0x5E" # CH0 ~ CH7
|
||||||
"0:0x5F" # CH8 ~ CH15
|
"0:0x5F" # CH8 ~ CH15
|
||||||
)
|
)
|
||||||
|
|
||||||
# Pre-commands to run before accessing each chip (empty = none)
|
# Pre-commands to run before accessing each chip (empty = none)
|
||||||
# Multiple commands separated by ;
|
# Multiple commands separated by ;
|
||||||
CHIP_PRE_CMD=(
|
CHIP_PRE_CMD=(
|
||||||
"" # SWB0 CONN14 (lo)
|
"" # SWB0 CONN14 (lo)
|
||||||
)
|
)
|
||||||
|
|
||||||
# Post-commands to run after accessing each chip (optional, empty = none)
|
# Post-commands to run after accessing each chip (optional, empty = none)
|
||||||
CHIP_POST_CMD=(
|
CHIP_POST_CMD=(
|
||||||
"" # SWB0 CONN14 (lo)
|
"" # SWB0 CONN14 (lo)
|
||||||
)
|
)
|
||||||
|
|
||||||
# ============================================================
|
# ============================================================
|
||||||
# chip1: SWB0 (CONN14)
|
# chip1: SWB0 (CONN14)
|
||||||
# ============================================================
|
# ============================================================
|
||||||
CH0_VNOM="0.75"; CH0_NET="P0V75_AVDD_7"
|
CH0_VNOM="0.75"; CH0_NET="P0V75_AVDD_7"
|
||||||
CH1_VNOM="1.5"; CH1_NET="P1V5_AVDD_7"
|
CH1_VNOM="1.5"; CH1_NET="P1V5_AVDD_7"
|
||||||
CH2_VNOM="0.9"; CH2_NET="P0V9_AVDD_7"
|
CH2_VNOM="0.9"; CH2_NET="P0V9_AVDD_7"
|
||||||
CH3_VNOM="1.8"; CH3_NET="P1V8_5"
|
CH3_VNOM="1.8"; CH3_NET="P1V8_5"
|
||||||
CH4_VNOM="1.8"; CH4_NET="P1V8_2"
|
CH4_VNOM="1.8"; CH4_NET="P1V8_2"
|
||||||
CH5_VNOM="3.3"; CH5_NET="PVDD3_3V_SYNTH_LDO_B2"
|
CH5_VNOM="3.3"; CH5_NET="PVDD3_3V_SYNTH_LDO_B2"
|
||||||
CH6_VNOM="3.3"; CH6_NET="PVDD3_3V_SYNTH_LDO_A2"
|
CH6_VNOM="3.3"; CH6_NET="PVDD3_3V_SYNTH_LDO_A2"
|
||||||
CH7_VNOM="3.3"; CH7_NET="PVDD3_3V_SYNTH_LDO_A1"
|
CH7_VNOM="3.3"; CH7_NET="PVDD3_3V_SYNTH_LDO_A1"
|
||||||
CH8_VNOM="1.5"; CH8_NET="PVDD1V5_TSC"
|
CH8_VNOM="1.5"; CH8_NET="PVDD1V5_TSC"
|
||||||
CH9_VNOM="1.5"; CH9_NET="PVDD1V5_ANLG"
|
CH9_VNOM="1.5"; CH9_NET="PVDD1V5_ANLG"
|
||||||
CH10_VNOM="-"; CH10_NET="NC"
|
CH10_VNOM="-"; CH10_NET="NC"
|
||||||
CH11_VNOM="-"; CH11_NET="NC"
|
CH11_VNOM="-"; CH11_NET="NC"
|
||||||
CH12_VNOM="1.5"; CH12_NET="PVDD1V5_1"
|
CH12_VNOM="1.5"; CH12_NET="PVDD1V5_1"
|
||||||
CH13_VNOM="-"; CH13_NET="NC"
|
CH13_VNOM="-"; CH13_NET="NC"
|
||||||
CH14_VNOM="1.8"; CH14_NET="P1V8_DVDDIO_1"
|
CH14_VNOM="1.8"; CH14_NET="P1V8_DVDDIO_1"
|
||||||
CH15_VNOM="0.75"; CH15_NET="P0V75_DVDD_7"
|
CH15_VNOM="0.75"; CH15_NET="P0V75_DVDD_7"
|
||||||
|
|||||||
+52
-52
@@ -1,52 +1,52 @@
|
|||||||
# Blanton Channel Settings
|
# Blanton Channel Settings
|
||||||
# Format: CH<n>_VNOM=voltage CH<n>_NET=net_name
|
# Format: CH<n>_VNOM=voltage CH<n>_NET=net_name
|
||||||
#
|
#
|
||||||
# Channel numbering (Script Channel, per Blanton_Margin_List):
|
# Channel numbering (Script Channel, per Blanton_Margin_List):
|
||||||
# ch_global / 8 -> CHIPS index (0~17)
|
# ch_global / 8 -> CHIPS index (0~17)
|
||||||
# ch_global % 8 -> page within LTC2977 (0~7)
|
# ch_global % 8 -> page within LTC2977 (0~7)
|
||||||
# One LTC2980 = two LTC2977 (8ch each), controlled via 2 I2C addresses.
|
# One LTC2980 = two LTC2977 (8ch each), controlled via 2 I2C addresses.
|
||||||
|
|
||||||
# --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
|
# --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
|
||||||
# it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
|
# it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
|
||||||
TRANSPORT="swb"
|
TRANSPORT="swb"
|
||||||
CB_I2C_CH=8 # CB F3 Ch8 = SWB0 CONN15/CONN16 (shared with CONN16, addr must differ)
|
CB_I2C_CH=8 # CB F3 Ch8 = SWB0 CONN15/CONN16 (shared with CONN16, addr must differ)
|
||||||
|
|
||||||
# --- I2C Configuration ---
|
# --- I2C Configuration ---
|
||||||
|
|
||||||
# Format: "bus:address" (8 channels per entry / per LTC2977)
|
# Format: "bus:address" (8 channels per entry / per LTC2977)
|
||||||
CHIPS=(
|
CHIPS=(
|
||||||
# chip1: SWB0 (CONN15)
|
# chip1: SWB0 (CONN15)
|
||||||
"0:0x62" # CH0 ~ CH7
|
"0:0x62" # CH0 ~ CH7
|
||||||
"0:0x63" # CH8 ~ CH15
|
"0:0x63" # CH8 ~ CH15
|
||||||
)
|
)
|
||||||
|
|
||||||
# Pre-commands to run before accessing each chip (empty = none)
|
# Pre-commands to run before accessing each chip (empty = none)
|
||||||
# Multiple commands separated by ;
|
# Multiple commands separated by ;
|
||||||
CHIP_PRE_CMD=(
|
CHIP_PRE_CMD=(
|
||||||
"" # SWB0 CONN15 (lo)
|
"" # SWB0 CONN15 (lo)
|
||||||
)
|
)
|
||||||
|
|
||||||
# Post-commands to run after accessing each chip (optional, empty = none)
|
# Post-commands to run after accessing each chip (optional, empty = none)
|
||||||
CHIP_POST_CMD=(
|
CHIP_POST_CMD=(
|
||||||
"" # SWB0 CONN15 (lo)
|
"" # SWB0 CONN15 (lo)
|
||||||
)
|
)
|
||||||
|
|
||||||
# ============================================================
|
# ============================================================
|
||||||
# chip1: SWB0 (CONN15)
|
# chip1: SWB0 (CONN15)
|
||||||
# ============================================================
|
# ============================================================
|
||||||
CH0_VNOM="1.5"; CH0_NET="P1V5_AVDD_55"
|
CH0_VNOM="1.5"; CH0_NET="P1V5_AVDD_55"
|
||||||
CH1_VNOM="0.9"; CH1_NET="P0V9_AVDD_55"
|
CH1_VNOM="0.9"; CH1_NET="P0V9_AVDD_55"
|
||||||
CH2_VNOM="0.75"; CH2_NET="P0V75_DVDD_63"
|
CH2_VNOM="0.75"; CH2_NET="P0V75_DVDD_63"
|
||||||
CH3_VNOM="0.75"; CH3_NET="P0V75_AVDD_63"
|
CH3_VNOM="0.75"; CH3_NET="P0V75_AVDD_63"
|
||||||
CH4_VNOM="1.5"; CH4_NET="P1V5_AVDD_63"
|
CH4_VNOM="1.5"; CH4_NET="P1V5_AVDD_63"
|
||||||
CH5_VNOM="0.9"; CH5_NET="P0V9_AVDD_63"
|
CH5_VNOM="0.9"; CH5_NET="P0V9_AVDD_63"
|
||||||
CH6_VNOM="3.3"; CH6_NET="PVDD3_3V_SYNTH_LDO_B3"
|
CH6_VNOM="3.3"; CH6_NET="PVDD3_3V_SYNTH_LDO_B3"
|
||||||
CH7_VNOM="1.5"; CH7_NET="PVDD1V5_3"
|
CH7_VNOM="1.5"; CH7_NET="PVDD1V5_3"
|
||||||
CH8_VNOM="0.85"; CH8_NET="P0V85_STBY"
|
CH8_VNOM="0.85"; CH8_NET="P0V85_STBY"
|
||||||
CH9_VNOM="1.8"; CH9_NET="P1V8_STBY"
|
CH9_VNOM="1.8"; CH9_NET="P1V8_STBY"
|
||||||
CH10_VNOM="-"; CH10_NET="NC"
|
CH10_VNOM="-"; CH10_NET="NC"
|
||||||
CH11_VNOM="3.3"; CH11_NET="P3V3_STBY"
|
CH11_VNOM="3.3"; CH11_NET="P3V3_STBY"
|
||||||
CH12_VNOM="0.9"; CH12_NET="PVDD0V9_2"
|
CH12_VNOM="0.9"; CH12_NET="PVDD0V9_2"
|
||||||
CH13_VNOM="0.75"; CH13_NET="P0V75_DVDD_55"
|
CH13_VNOM="0.75"; CH13_NET="P0V75_DVDD_55"
|
||||||
CH14_VNOM="0.75"; CH14_NET="P0V75_AVDD_55"
|
CH14_VNOM="0.75"; CH14_NET="P0V75_AVDD_55"
|
||||||
CH15_VNOM="1.8"; CH15_NET="P1V8_DVDDIO_4"
|
CH15_VNOM="1.8"; CH15_NET="P1V8_DVDDIO_4"
|
||||||
|
|||||||
+52
-52
@@ -1,52 +1,52 @@
|
|||||||
# Blanton Channel Settings
|
# Blanton Channel Settings
|
||||||
# Format: CH<n>_VNOM=voltage CH<n>_NET=net_name
|
# Format: CH<n>_VNOM=voltage CH<n>_NET=net_name
|
||||||
#
|
#
|
||||||
# Channel numbering (Script Channel, per Blanton_Margin_List):
|
# Channel numbering (Script Channel, per Blanton_Margin_List):
|
||||||
# ch_global / 8 -> CHIPS index (0~17)
|
# ch_global / 8 -> CHIPS index (0~17)
|
||||||
# ch_global % 8 -> page within LTC2977 (0~7)
|
# ch_global % 8 -> page within LTC2977 (0~7)
|
||||||
# One LTC2980 = two LTC2977 (8ch each), controlled via 2 I2C addresses.
|
# One LTC2980 = two LTC2977 (8ch each), controlled via 2 I2C addresses.
|
||||||
|
|
||||||
# --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
|
# --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
|
||||||
# it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
|
# it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
|
||||||
TRANSPORT="swb"
|
TRANSPORT="swb"
|
||||||
CB_I2C_CH=8 # CB F3 Ch8 = SWB0 CONN15/CONN16 (shared with CONN15, addr must differ)
|
CB_I2C_CH=8 # CB F3 Ch8 = SWB0 CONN15/CONN16 (shared with CONN15, addr must differ)
|
||||||
|
|
||||||
# --- I2C Configuration ---
|
# --- I2C Configuration ---
|
||||||
|
|
||||||
# Format: "bus:address" (8 channels per entry / per LTC2977)
|
# Format: "bus:address" (8 channels per entry / per LTC2977)
|
||||||
CHIPS=(
|
CHIPS=(
|
||||||
# chip1: SWB0 (CONN16)
|
# chip1: SWB0 (CONN16)
|
||||||
"0:0x64" # CH0 ~ CH7
|
"0:0x64" # CH0 ~ CH7
|
||||||
"0:0x65" # CH8 ~ CH15
|
"0:0x65" # CH8 ~ CH15
|
||||||
)
|
)
|
||||||
|
|
||||||
# Pre-commands to run before accessing each chip (empty = none)
|
# Pre-commands to run before accessing each chip (empty = none)
|
||||||
# Multiple commands separated by ;
|
# Multiple commands separated by ;
|
||||||
CHIP_PRE_CMD=(
|
CHIP_PRE_CMD=(
|
||||||
"" # SWB0 CONN16 (lo)
|
"" # SWB0 CONN16 (lo)
|
||||||
)
|
)
|
||||||
|
|
||||||
# Post-commands to run after accessing each chip (optional, empty = none)
|
# Post-commands to run after accessing each chip (optional, empty = none)
|
||||||
CHIP_POST_CMD=(
|
CHIP_POST_CMD=(
|
||||||
"" # SWB0 CONN16 (lo)
|
"" # SWB0 CONN16 (lo)
|
||||||
)
|
)
|
||||||
|
|
||||||
# ============================================================
|
# ============================================================
|
||||||
# chip1: SWB0 (CONN16)
|
# chip1: SWB0 (CONN16)
|
||||||
# ============================================================
|
# ============================================================
|
||||||
CH0_VNOM="1.5"; CH0_NET="PVDD1V5_0"
|
CH0_VNOM="1.5"; CH0_NET="PVDD1V5_0"
|
||||||
CH1_VNOM="1.8"; CH1_NET="P1V8_4"
|
CH1_VNOM="1.8"; CH1_NET="P1V8_4"
|
||||||
CH2_VNOM="3.3"; CH2_NET="PVDD3_3V_SYNTH_LDO_B5"
|
CH2_VNOM="3.3"; CH2_NET="PVDD3_3V_SYNTH_LDO_B5"
|
||||||
CH3_VNOM="3.3"; CH3_NET="PVDD3_3V_SYNTH_LDO_A5"
|
CH3_VNOM="3.3"; CH3_NET="PVDD3_3V_SYNTH_LDO_A5"
|
||||||
CH4_VNOM="3.3"; CH4_NET="PVDD3_3V_SYNTH_LDO_B4"
|
CH4_VNOM="3.3"; CH4_NET="PVDD3_3V_SYNTH_LDO_B4"
|
||||||
CH5_VNOM="3.3"; CH5_NET="PVDD3_3V_SYNTH_LDO_A4"
|
CH5_VNOM="3.3"; CH5_NET="PVDD3_3V_SYNTH_LDO_A4"
|
||||||
CH6_VNOM="3.3"; CH6_NET="P3V3"
|
CH6_VNOM="3.3"; CH6_NET="P3V3"
|
||||||
CH7_VNOM="0.8"; CH7_NET="PVDD0_8V_T3"
|
CH7_VNOM="0.8"; CH7_NET="PVDD0_8V_T3"
|
||||||
CH8_VNOM="0.75"; CH8_NET="P0V75_DVDD_1"
|
CH8_VNOM="0.75"; CH8_NET="P0V75_DVDD_1"
|
||||||
CH9_VNOM="0.75"; CH9_NET="P0V75_AVDD_1"
|
CH9_VNOM="0.75"; CH9_NET="P0V75_AVDD_1"
|
||||||
CH10_VNOM="1.5"; CH10_NET="P1V5_AVDD_1"
|
CH10_VNOM="1.5"; CH10_NET="P1V5_AVDD_1"
|
||||||
CH11_VNOM="0.9"; CH11_NET="P0V9_AVDD_1"
|
CH11_VNOM="0.9"; CH11_NET="P0V9_AVDD_1"
|
||||||
CH12_VNOM="0.9"; CH12_NET="PVDD0V9_0"
|
CH12_VNOM="0.9"; CH12_NET="PVDD0V9_0"
|
||||||
CH13_VNOM="0.9"; CH13_NET="PVDD0V9_1"
|
CH13_VNOM="0.9"; CH13_NET="PVDD0V9_1"
|
||||||
CH14_VNOM="0.9"; CH14_NET="PVDD0V9_3"
|
CH14_VNOM="0.9"; CH14_NET="PVDD0V9_3"
|
||||||
CH15_VNOM="1.2"; CH15_NET="PVDD1V2_T3"
|
CH15_VNOM="1.2"; CH15_NET="PVDD1V2_T3"
|
||||||
|
|||||||
+52
-52
@@ -1,52 +1,52 @@
|
|||||||
# Blanton Channel Settings
|
# Blanton Channel Settings
|
||||||
# Format: CH<n>_VNOM=voltage CH<n>_NET=net_name
|
# Format: CH<n>_VNOM=voltage CH<n>_NET=net_name
|
||||||
#
|
#
|
||||||
# Channel numbering (Script Channel, per Blanton_Margin_List):
|
# Channel numbering (Script Channel, per Blanton_Margin_List):
|
||||||
# ch_global / 8 -> CHIPS index (0~17)
|
# ch_global / 8 -> CHIPS index (0~17)
|
||||||
# ch_global % 8 -> page within LTC2977 (0~7)
|
# ch_global % 8 -> page within LTC2977 (0~7)
|
||||||
# One LTC2980 = two LTC2977 (8ch each), controlled via 2 I2C addresses.
|
# One LTC2980 = two LTC2977 (8ch each), controlled via 2 I2C addresses.
|
||||||
|
|
||||||
# --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
|
# --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
|
||||||
# it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
|
# it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
|
||||||
TRANSPORT="swb"
|
TRANSPORT="swb"
|
||||||
CB_I2C_CH=7 # CB F3 Ch7 = SWB1 CONN13/CONN14 (shared with CONN14, addr must differ)
|
CB_I2C_CH=7 # CB F3 Ch7 = SWB1 CONN13/CONN14 (shared with CONN14, addr must differ)
|
||||||
|
|
||||||
# --- I2C Configuration ---
|
# --- I2C Configuration ---
|
||||||
|
|
||||||
# Format: "bus:address" (8 channels per entry / per LTC2977)
|
# Format: "bus:address" (8 channels per entry / per LTC2977)
|
||||||
CHIPS=(
|
CHIPS=(
|
||||||
# chip1: SWB1 (CONN13)
|
# chip1: SWB1 (CONN13)
|
||||||
"1:0x5C" # CH0 ~ CH7
|
"1:0x5C" # CH0 ~ CH7
|
||||||
"1:0x5D" # CH8 ~ CH15
|
"1:0x5D" # CH8 ~ CH15
|
||||||
)
|
)
|
||||||
|
|
||||||
# Pre-commands to run before accessing each chip (empty = none)
|
# Pre-commands to run before accessing each chip (empty = none)
|
||||||
# Multiple commands separated by ;
|
# Multiple commands separated by ;
|
||||||
CHIP_PRE_CMD=(
|
CHIP_PRE_CMD=(
|
||||||
"" # SWB1 CONN13 (lo)
|
"" # SWB1 CONN13 (lo)
|
||||||
)
|
)
|
||||||
|
|
||||||
# Post-commands to run after accessing each chip (optional, empty = none)
|
# Post-commands to run after accessing each chip (optional, empty = none)
|
||||||
CHIP_POST_CMD=(
|
CHIP_POST_CMD=(
|
||||||
"" # SWB1 CONN13 (lo)
|
"" # SWB1 CONN13 (lo)
|
||||||
)
|
)
|
||||||
|
|
||||||
# ============================================================
|
# ============================================================
|
||||||
# chip1: SWB1 (CONN13)
|
# chip1: SWB1 (CONN13)
|
||||||
# ============================================================
|
# ============================================================
|
||||||
CH0_VNOM="0.75"; CH0_NET="P0V75_DVDD_47"
|
CH0_VNOM="0.75"; CH0_NET="P0V75_DVDD_47"
|
||||||
CH1_VNOM="0.75"; CH1_NET="P0V75_AVDD_47"
|
CH1_VNOM="0.75"; CH1_NET="P0V75_AVDD_47"
|
||||||
CH2_VNOM="1.5"; CH2_NET="P1V5_AVDD_47"
|
CH2_VNOM="1.5"; CH2_NET="P1V5_AVDD_47"
|
||||||
CH3_VNOM="0.9"; CH3_NET="P0V9_AVDD_47"
|
CH3_VNOM="0.9"; CH3_NET="P0V9_AVDD_47"
|
||||||
CH4_VNOM="1.8"; CH4_NET="P1V8_1"
|
CH4_VNOM="1.8"; CH4_NET="P1V8_1"
|
||||||
CH5_VNOM="3.3"; CH5_NET="PVDD3_3V_SYNTH_LDO_A3"
|
CH5_VNOM="3.3"; CH5_NET="PVDD3_3V_SYNTH_LDO_A3"
|
||||||
CH6_VNOM="3.3"; CH6_NET="PVDD3_3V_SYNTH_LDO_B1"
|
CH6_VNOM="3.3"; CH6_NET="PVDD3_3V_SYNTH_LDO_B1"
|
||||||
CH7_VNOM="1.8"; CH7_NET="P1V8_3"
|
CH7_VNOM="1.8"; CH7_NET="P1V8_3"
|
||||||
CH8_VNOM="1.8"; CH8_NET="P1V8_DVDDIO_3"
|
CH8_VNOM="1.8"; CH8_NET="P1V8_DVDDIO_3"
|
||||||
CH9_VNOM="0.75"; CH9_NET="P0V75_DVDD_39"
|
CH9_VNOM="0.75"; CH9_NET="P0V75_DVDD_39"
|
||||||
CH10_VNOM="0.75"; CH10_NET="P0V75_AVDD_39"
|
CH10_VNOM="0.75"; CH10_NET="P0V75_AVDD_39"
|
||||||
CH11_VNOM="1.5"; CH11_NET="P1V5_AVDD_39"
|
CH11_VNOM="1.5"; CH11_NET="P1V5_AVDD_39"
|
||||||
CH12_VNOM="0.9"; CH12_NET="P0V9_AVDD_39"
|
CH12_VNOM="0.9"; CH12_NET="P0V9_AVDD_39"
|
||||||
CH13_VNOM="1.5"; CH13_NET="PVDD1V5_2"
|
CH13_VNOM="1.5"; CH13_NET="PVDD1V5_2"
|
||||||
CH14_VNOM="1.8"; CH14_NET="PVDD1V8_DUT"
|
CH14_VNOM="1.8"; CH14_NET="PVDD1V8_DUT"
|
||||||
CH15_VNOM="1.2"; CH15_NET="PVDD_MDIO"
|
CH15_VNOM="1.2"; CH15_NET="PVDD_MDIO"
|
||||||
|
|||||||
+52
-52
@@ -1,52 +1,52 @@
|
|||||||
# Blanton Channel Settings
|
# Blanton Channel Settings
|
||||||
# Format: CH<n>_VNOM=voltage CH<n>_NET=net_name
|
# Format: CH<n>_VNOM=voltage CH<n>_NET=net_name
|
||||||
#
|
#
|
||||||
# Channel numbering (Script Channel, per Blanton_Margin_List):
|
# Channel numbering (Script Channel, per Blanton_Margin_List):
|
||||||
# ch_global / 8 -> CHIPS index (0~17)
|
# ch_global / 8 -> CHIPS index (0~17)
|
||||||
# ch_global % 8 -> page within LTC2977 (0~7)
|
# ch_global % 8 -> page within LTC2977 (0~7)
|
||||||
# One LTC2980 = two LTC2977 (8ch each), controlled via 2 I2C addresses.
|
# One LTC2980 = two LTC2977 (8ch each), controlled via 2 I2C addresses.
|
||||||
|
|
||||||
# --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
|
# --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
|
||||||
# it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
|
# it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
|
||||||
TRANSPORT="swb"
|
TRANSPORT="swb"
|
||||||
CB_I2C_CH=7 # CB F3 Ch7 = SWB1 CONN13/CONN14 (shared with CONN13, addr must differ)
|
CB_I2C_CH=7 # CB F3 Ch7 = SWB1 CONN13/CONN14 (shared with CONN13, addr must differ)
|
||||||
|
|
||||||
# --- I2C Configuration ---
|
# --- I2C Configuration ---
|
||||||
|
|
||||||
# Format: "bus:address" (8 channels per entry / per LTC2977)
|
# Format: "bus:address" (8 channels per entry / per LTC2977)
|
||||||
CHIPS=(
|
CHIPS=(
|
||||||
# chip1: SWB1 (CONN14)
|
# chip1: SWB1 (CONN14)
|
||||||
"1:0x5E" # CH0 ~ CH7
|
"1:0x5E" # CH0 ~ CH7
|
||||||
"1:0x5F" # CH8 ~ CH15
|
"1:0x5F" # CH8 ~ CH15
|
||||||
)
|
)
|
||||||
|
|
||||||
# Pre-commands to run before accessing each chip (empty = none)
|
# Pre-commands to run before accessing each chip (empty = none)
|
||||||
# Multiple commands separated by ;
|
# Multiple commands separated by ;
|
||||||
CHIP_PRE_CMD=(
|
CHIP_PRE_CMD=(
|
||||||
"" # SWB1 CONN14 (lo)
|
"" # SWB1 CONN14 (lo)
|
||||||
)
|
)
|
||||||
|
|
||||||
# Post-commands to run after accessing each chip (optional, empty = none)
|
# Post-commands to run after accessing each chip (optional, empty = none)
|
||||||
CHIP_POST_CMD=(
|
CHIP_POST_CMD=(
|
||||||
"" # SWB1 CONN14 (lo)
|
"" # SWB1 CONN14 (lo)
|
||||||
)
|
)
|
||||||
|
|
||||||
# ============================================================
|
# ============================================================
|
||||||
# chip1: SWB1 (CONN14)
|
# chip1: SWB1 (CONN14)
|
||||||
# ============================================================
|
# ============================================================
|
||||||
CH0_VNOM="0.75"; CH0_NET="P0V75_AVDD_7"
|
CH0_VNOM="0.75"; CH0_NET="P0V75_AVDD_7"
|
||||||
CH1_VNOM="1.5"; CH1_NET="P1V5_AVDD_7"
|
CH1_VNOM="1.5"; CH1_NET="P1V5_AVDD_7"
|
||||||
CH2_VNOM="0.9"; CH2_NET="P0V9_AVDD_7"
|
CH2_VNOM="0.9"; CH2_NET="P0V9_AVDD_7"
|
||||||
CH3_VNOM="1.8"; CH3_NET="P1V8_5"
|
CH3_VNOM="1.8"; CH3_NET="P1V8_5"
|
||||||
CH4_VNOM="1.8"; CH4_NET="P1V8_2"
|
CH4_VNOM="1.8"; CH4_NET="P1V8_2"
|
||||||
CH5_VNOM="3.3"; CH5_NET="PVDD3_3V_SYNTH_LDO_B2"
|
CH5_VNOM="3.3"; CH5_NET="PVDD3_3V_SYNTH_LDO_B2"
|
||||||
CH6_VNOM="3.3"; CH6_NET="PVDD3_3V_SYNTH_LDO_A2"
|
CH6_VNOM="3.3"; CH6_NET="PVDD3_3V_SYNTH_LDO_A2"
|
||||||
CH7_VNOM="3.3"; CH7_NET="PVDD3_3V_SYNTH_LDO_A1"
|
CH7_VNOM="3.3"; CH7_NET="PVDD3_3V_SYNTH_LDO_A1"
|
||||||
CH8_VNOM="1.5"; CH8_NET="PVDD1V5_TSC"
|
CH8_VNOM="1.5"; CH8_NET="PVDD1V5_TSC"
|
||||||
CH9_VNOM="1.5"; CH9_NET="PVDD1V5_ANLG"
|
CH9_VNOM="1.5"; CH9_NET="PVDD1V5_ANLG"
|
||||||
CH10_VNOM="-"; CH10_NET="NC"
|
CH10_VNOM="-"; CH10_NET="NC"
|
||||||
CH11_VNOM="-"; CH11_NET="NC"
|
CH11_VNOM="-"; CH11_NET="NC"
|
||||||
CH12_VNOM="1.5"; CH12_NET="PVDD1V5_1"
|
CH12_VNOM="1.5"; CH12_NET="PVDD1V5_1"
|
||||||
CH13_VNOM="-"; CH13_NET="NC"
|
CH13_VNOM="-"; CH13_NET="NC"
|
||||||
CH14_VNOM="1.8"; CH14_NET="P1V8_DVDDIO_1"
|
CH14_VNOM="1.8"; CH14_NET="P1V8_DVDDIO_1"
|
||||||
CH15_VNOM="0.75"; CH15_NET="P0V75_DVDD_7"
|
CH15_VNOM="0.75"; CH15_NET="P0V75_DVDD_7"
|
||||||
|
|||||||
+52
-52
@@ -1,52 +1,52 @@
|
|||||||
# Blanton Channel Settings
|
# Blanton Channel Settings
|
||||||
# Format: CH<n>_VNOM=voltage CH<n>_NET=net_name
|
# Format: CH<n>_VNOM=voltage CH<n>_NET=net_name
|
||||||
#
|
#
|
||||||
# Channel numbering (Script Channel, per Blanton_Margin_List):
|
# Channel numbering (Script Channel, per Blanton_Margin_List):
|
||||||
# ch_global / 8 -> CHIPS index (0~17)
|
# ch_global / 8 -> CHIPS index (0~17)
|
||||||
# ch_global % 8 -> page within LTC2977 (0~7)
|
# ch_global % 8 -> page within LTC2977 (0~7)
|
||||||
# One LTC2980 = two LTC2977 (8ch each), controlled via 2 I2C addresses.
|
# One LTC2980 = two LTC2977 (8ch each), controlled via 2 I2C addresses.
|
||||||
|
|
||||||
# --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
|
# --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
|
||||||
# it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
|
# it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
|
||||||
TRANSPORT="swb"
|
TRANSPORT="swb"
|
||||||
CB_I2C_CH=9 # CB F3 Ch9 = SWB1 CONN15/CONN16 (shared with CONN16, addr must differ)
|
CB_I2C_CH=9 # CB F3 Ch9 = SWB1 CONN15/CONN16 (shared with CONN16, addr must differ)
|
||||||
|
|
||||||
# --- I2C Configuration ---
|
# --- I2C Configuration ---
|
||||||
|
|
||||||
# Format: "bus:address" (8 channels per entry / per LTC2977)
|
# Format: "bus:address" (8 channels per entry / per LTC2977)
|
||||||
CHIPS=(
|
CHIPS=(
|
||||||
# chip1: SWB1 (CONN15)
|
# chip1: SWB1 (CONN15)
|
||||||
"1:0x62" # CH0 ~ CH7
|
"1:0x62" # CH0 ~ CH7
|
||||||
"1:0x63" # CH8 ~ CH15
|
"1:0x63" # CH8 ~ CH15
|
||||||
)
|
)
|
||||||
|
|
||||||
# Pre-commands to run before accessing each chip (empty = none)
|
# Pre-commands to run before accessing each chip (empty = none)
|
||||||
# Multiple commands separated by ;
|
# Multiple commands separated by ;
|
||||||
CHIP_PRE_CMD=(
|
CHIP_PRE_CMD=(
|
||||||
"" # SWB1 CONN15 (lo)
|
"" # SWB1 CONN15 (lo)
|
||||||
)
|
)
|
||||||
|
|
||||||
# Post-commands to run after accessing each chip (optional, empty = none)
|
# Post-commands to run after accessing each chip (optional, empty = none)
|
||||||
CHIP_POST_CMD=(
|
CHIP_POST_CMD=(
|
||||||
"" # SWB1 CONN15 (lo)
|
"" # SWB1 CONN15 (lo)
|
||||||
)
|
)
|
||||||
|
|
||||||
# ============================================================
|
# ============================================================
|
||||||
# chip1: SWB1 (CONN15)
|
# chip1: SWB1 (CONN15)
|
||||||
# ============================================================
|
# ============================================================
|
||||||
CH0_VNOM="1.5"; CH0_NET="P1V5_AVDD_55"
|
CH0_VNOM="1.5"; CH0_NET="P1V5_AVDD_55"
|
||||||
CH1_VNOM="0.9"; CH1_NET="P0V9_AVDD_55"
|
CH1_VNOM="0.9"; CH1_NET="P0V9_AVDD_55"
|
||||||
CH2_VNOM="0.75"; CH2_NET="P0V75_DVDD_63"
|
CH2_VNOM="0.75"; CH2_NET="P0V75_DVDD_63"
|
||||||
CH3_VNOM="0.75"; CH3_NET="P0V75_AVDD_63"
|
CH3_VNOM="0.75"; CH3_NET="P0V75_AVDD_63"
|
||||||
CH4_VNOM="1.5"; CH4_NET="P1V5_AVDD_63"
|
CH4_VNOM="1.5"; CH4_NET="P1V5_AVDD_63"
|
||||||
CH5_VNOM="0.9"; CH5_NET="P0V9_AVDD_63"
|
CH5_VNOM="0.9"; CH5_NET="P0V9_AVDD_63"
|
||||||
CH6_VNOM="3.3"; CH6_NET="PVDD3_3V_SYNTH_LDO_B3"
|
CH6_VNOM="3.3"; CH6_NET="PVDD3_3V_SYNTH_LDO_B3"
|
||||||
CH7_VNOM="1.5"; CH7_NET="PVDD1V5_3"
|
CH7_VNOM="1.5"; CH7_NET="PVDD1V5_3"
|
||||||
CH8_VNOM="0.85"; CH8_NET="P0V85_STBY"
|
CH8_VNOM="0.85"; CH8_NET="P0V85_STBY"
|
||||||
CH9_VNOM="1.8"; CH9_NET="P1V8_STBY"
|
CH9_VNOM="1.8"; CH9_NET="P1V8_STBY"
|
||||||
CH10_VNOM="-"; CH10_NET="NC"
|
CH10_VNOM="-"; CH10_NET="NC"
|
||||||
CH11_VNOM="3.3"; CH11_NET="P3V3_STBY"
|
CH11_VNOM="3.3"; CH11_NET="P3V3_STBY"
|
||||||
CH12_VNOM="0.9"; CH12_NET="PVDD0V9_2"
|
CH12_VNOM="0.9"; CH12_NET="PVDD0V9_2"
|
||||||
CH13_VNOM="0.75"; CH13_NET="P0V75_DVDD_55"
|
CH13_VNOM="0.75"; CH13_NET="P0V75_DVDD_55"
|
||||||
CH14_VNOM="0.75"; CH14_NET="P0V75_AVDD_55"
|
CH14_VNOM="0.75"; CH14_NET="P0V75_AVDD_55"
|
||||||
CH15_VNOM="1.8"; CH15_NET="P1V8_DVDDIO_4"
|
CH15_VNOM="1.8"; CH15_NET="P1V8_DVDDIO_4"
|
||||||
|
|||||||
+52
-52
@@ -1,52 +1,52 @@
|
|||||||
# Blanton Channel Settings
|
# Blanton Channel Settings
|
||||||
# Format: CH<n>_VNOM=voltage CH<n>_NET=net_name
|
# Format: CH<n>_VNOM=voltage CH<n>_NET=net_name
|
||||||
#
|
#
|
||||||
# Channel numbering (Script Channel, per Blanton_Margin_List):
|
# Channel numbering (Script Channel, per Blanton_Margin_List):
|
||||||
# ch_global / 8 -> CHIPS index (0~17)
|
# ch_global / 8 -> CHIPS index (0~17)
|
||||||
# ch_global % 8 -> page within LTC2977 (0~7)
|
# ch_global % 8 -> page within LTC2977 (0~7)
|
||||||
# One LTC2980 = two LTC2977 (8ch each), controlled via 2 I2C addresses.
|
# One LTC2980 = two LTC2977 (8ch each), controlled via 2 I2C addresses.
|
||||||
|
|
||||||
# --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
|
# --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
|
||||||
# it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
|
# it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
|
||||||
TRANSPORT="swb"
|
TRANSPORT="swb"
|
||||||
CB_I2C_CH=9 # CB F3 Ch9 = SWB1 CONN15/CONN16 (shared with CONN15, addr must differ)
|
CB_I2C_CH=9 # CB F3 Ch9 = SWB1 CONN15/CONN16 (shared with CONN15, addr must differ)
|
||||||
|
|
||||||
# --- I2C Configuration ---
|
# --- I2C Configuration ---
|
||||||
|
|
||||||
# Format: "bus:address" (8 channels per entry / per LTC2977)
|
# Format: "bus:address" (8 channels per entry / per LTC2977)
|
||||||
CHIPS=(
|
CHIPS=(
|
||||||
# chip1: SWB1 (CONN16)
|
# chip1: SWB1 (CONN16)
|
||||||
"1:0x64" # CH0 ~ CH7
|
"1:0x64" # CH0 ~ CH7
|
||||||
"1:0x65" # CH8 ~ CH15
|
"1:0x65" # CH8 ~ CH15
|
||||||
)
|
)
|
||||||
|
|
||||||
# Pre-commands to run before accessing each chip (empty = none)
|
# Pre-commands to run before accessing each chip (empty = none)
|
||||||
# Multiple commands separated by ;
|
# Multiple commands separated by ;
|
||||||
CHIP_PRE_CMD=(
|
CHIP_PRE_CMD=(
|
||||||
"" # SWB1 CONN16 (lo)
|
"" # SWB1 CONN16 (lo)
|
||||||
)
|
)
|
||||||
|
|
||||||
# Post-commands to run after accessing each chip (optional, empty = none)
|
# Post-commands to run after accessing each chip (optional, empty = none)
|
||||||
CHIP_POST_CMD=(
|
CHIP_POST_CMD=(
|
||||||
"" # SWB1 CONN16 (lo)
|
"" # SWB1 CONN16 (lo)
|
||||||
)
|
)
|
||||||
|
|
||||||
# ============================================================
|
# ============================================================
|
||||||
# chip1: SWB1 (CONN16)
|
# chip1: SWB1 (CONN16)
|
||||||
# ============================================================
|
# ============================================================
|
||||||
CH0_VNOM="1.5"; CH0_NET="PVDD1V5_0"
|
CH0_VNOM="1.5"; CH0_NET="PVDD1V5_0"
|
||||||
CH1_VNOM="1.8"; CH1_NET="P1V8_4"
|
CH1_VNOM="1.8"; CH1_NET="P1V8_4"
|
||||||
CH2_VNOM="3.3"; CH2_NET="PVDD3_3V_SYNTH_LDO_B5"
|
CH2_VNOM="3.3"; CH2_NET="PVDD3_3V_SYNTH_LDO_B5"
|
||||||
CH3_VNOM="3.3"; CH3_NET="PVDD3_3V_SYNTH_LDO_A5"
|
CH3_VNOM="3.3"; CH3_NET="PVDD3_3V_SYNTH_LDO_A5"
|
||||||
CH4_VNOM="3.3"; CH4_NET="PVDD3_3V_SYNTH_LDO_B4"
|
CH4_VNOM="3.3"; CH4_NET="PVDD3_3V_SYNTH_LDO_B4"
|
||||||
CH5_VNOM="3.3"; CH5_NET="PVDD3_3V_SYNTH_LDO_A4"
|
CH5_VNOM="3.3"; CH5_NET="PVDD3_3V_SYNTH_LDO_A4"
|
||||||
CH6_VNOM="3.3"; CH6_NET="P3V3"
|
CH6_VNOM="3.3"; CH6_NET="P3V3"
|
||||||
CH7_VNOM="0.8"; CH7_NET="PVDD0_8V_T3"
|
CH7_VNOM="0.8"; CH7_NET="PVDD0_8V_T3"
|
||||||
CH8_VNOM="0.75"; CH8_NET="P0V75_DVDD_1"
|
CH8_VNOM="0.75"; CH8_NET="P0V75_DVDD_1"
|
||||||
CH9_VNOM="0.75"; CH9_NET="P0V75_AVDD_1"
|
CH9_VNOM="0.75"; CH9_NET="P0V75_AVDD_1"
|
||||||
CH10_VNOM="1.5"; CH10_NET="P1V5_AVDD_1"
|
CH10_VNOM="1.5"; CH10_NET="P1V5_AVDD_1"
|
||||||
CH11_VNOM="0.9"; CH11_NET="P0V9_AVDD_1"
|
CH11_VNOM="0.9"; CH11_NET="P0V9_AVDD_1"
|
||||||
CH12_VNOM="0.9"; CH12_NET="PVDD0V9_0"
|
CH12_VNOM="0.9"; CH12_NET="PVDD0V9_0"
|
||||||
CH13_VNOM="0.9"; CH13_NET="PVDD0V9_1"
|
CH13_VNOM="0.9"; CH13_NET="PVDD0V9_1"
|
||||||
CH14_VNOM="0.9"; CH14_NET="PVDD0V9_3"
|
CH14_VNOM="0.9"; CH14_NET="PVDD0V9_3"
|
||||||
CH15_VNOM="1.2"; CH15_NET="PVDD1V2_T3"
|
CH15_VNOM="1.2"; CH15_NET="PVDD1V2_T3"
|
||||||
|
|||||||
Reference in New Issue
Block a user