Commit Graph
55 Commits
Author SHA1 Message Date
etwen 9d61b1aa43 docs(status): Add TTL script status sheet 20260817 2026-08-17 16:32:44 +08:00
etwen 071244fde1 feat(traffic): Add SWB loopback line-speed traffic tool
Blanton_Script/blanton_traffic_linespeed.sh V0.3.2 drives the whole
loopback traffic run from the DUT shell via bcmcmd, for both switch
boards (unit 0 and 1):

- init  : vlan remove 1 pbm=cd, then create/add the 108 loopback
          pairs (VLAN 30..137, cdN <-> cdN+32)
- clear : clear c
- show  : show c (raw)
- start : tx <count> length=<len> VLantag=<vid> per VLAN
- stop  : remove the pairs, optional --destroy
- ps    : port status of the cabled ports
- report: parse the show c MIB_TPOK/MIB_RPOK counters and lay them
          out one pair per block with a cross-check verdict
          (cdA.TX == cdB.RX and cdA.RX == cdB.TX), PASS green /
          FAIL red / NA yellow, --tolerance for snapshot skew,
          --tsv, --raw and -f <log> for offline analysis; the raw
          capture is kept under /tmp
- run   : ps -> init -> clear -> start -> report

Options -u/-c/-l/-p/-T/-d/-n and a sourceable function API, in the
style of the other blanton_*.sh tools. Command output matches the
former Tera Term macros byte for byte; report output matches
tools/bcm_mibpair_report_V1.1.0.py, added here as the off-box
equivalent, together with the raw bcmcmd command lists under tools/.

ScriptA sources the tool, ScriptB runs ps/init/clear/show/start and
drops stress_hhmd and stress_pcie, ScriptC stops the traffic and
prints the pair counter report.
2026-08-17 16:32:43 +08:00
etwen 9bf4291d17 feat(fpga): Auto-detect CB FPGA BDF at source time
blanton_fpga_pcimem.sh V1.5.0.

The four FUNCT0..3_RES sysfs paths were hard-coded and had to be
edited for every DUT, because the CB FPGA's BDF changes with the
PCIe enumeration (0000:03:00.x / 0000:05:00.x seen so far).

Detection order at source time: FPGA_BDF override -> sysfs scan for
vendor 0x1590 with all four functions exposing resource0 -> lspci
-Dnn name/id match -> FPGA_BDF_FALLBACK. Adds fpga_rescan for a
DUT swap, FPGA_BDF / FPGA_VENDOR_ID / FPGA_LSPCI_MATCH overrides,
FPGA_BDF_ACTIVE reporting and FPGA_QUIET. Detection runs once, so
cb_fpga / pmc / icb / swb keep zero per-command overhead.
2026-08-17 16:32:42 +08:00
etwen 725f51681a feat(ttl): Add leakage status to PMON snapshot, bump A/B/C to V1.0.2
- utils/setup_pmon.ttl: add 'show platform leak status' and 'leak channels'
- Script A: move setup_pmon include into the TAKE DATA block
- Script B: soak loop now reuses utils/setup_pmon.ttl instead of inline fan/temperature
- Script C: fix header title (was 'Script B')
2026-08-17 10:06:24 +08:00
etwenandClaude Opus 5 24c704c667 docs(arch): Add ARCHITECTURE.md and CLAUDE.md, init repo
Bring the Blanton Tera Term TTL test suite under version control and
document how the pieces fit together.

- ARCHITECTURE.md: A/B/C script roles, host-to-DUT-to-FPGA data path,
  config/settings/profile data models, PCIe AER + EDAC topology table,
  10 key constraints, and 6 development phases derived from the
  Status_20260814 spreadsheet's On-Going items
- CLAUDE.md: stack, smoke-test commands, conventions, and the hardware
  footguns (per-unit BDF, VSPI vs VI2C timing, repeated START,
  STORE_USER_ALL, ARB_LOST false positives)
- secret/: gitignored credential store with README + .example template,
  so the DUT login stops living in 1_Blanton_Script_A.ttl
- .gitignore: secret/*, For_AI/, *.log, publish/, *.DSN

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_014RetWKFZFG1ZHcitQAyhwM
2026-08-17 08:52:11 +08:00