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• V1.2.2 b911ccd658

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  v1.2.2 — The 100G uplink joins the BER sweep, and a boot cycle that can pull the power Stable

  etwen released this 2026-09-15 21:27:40 +08:00 | 18 commits to main since this release

  ✨ New features

  The BER sweep now measures port 268, the 100G uplink

  • The port list ran 256-259 straight to 270-308, so ce0(268) — the 100G uplink — was never in it. It is now its own group alongside the 200G ports.
  • The summary gives each unit three rows: 200G ports, 100G p268, and TOTAL. Unit 0 and unit 1 each have their own ce0(268), and a marginal uplink lane averaged into 432 others is invisible; on its own row it is not.
  • A group that reports no lane at all now counts as a failure, not a pass. Silence on the port under test is the easiest way to ship a green report that measured nothing.

  Script 5 is now a boot cycle, warm or cold

  • 5_Blanton_Script_Reboot_Cycle.ttl → 5_Blanton_Script_Boot_Cycle.ttl, with EN_Cold_Warm_boot in config.ttl choosing: 1 = reboot (warm), 2 = a cold cycle by writing the CB FPGA, 0 = neither.
  • The log file and the per-round banner are named after the kind of boot: Blanton_Reboot_Cycle_<ts>.log / Reboot Cycle : N, or Blanton_Power_Cycle_<ts>.log / Power Cycle : N.
  • Both stress logs are removed before each run. qfx5252-stress-* appends to its --log and the macro cats the whole thing, so every cycle was printing back everything the earlier cycles had written — 289 lines at cycle 1 and 36,555 by cycle 199. At roughly 6.2 ms a line on a 115200 console that accounted for +212 s of the +214 s the cycle grew over a 199-cycle run. The DUT was never getting slower.

  bcm_100g_dsc_cycle.sh — 100G link down/up cycling with SerDes capture

  • Tuning once, then N cycles of port 268 en=0 → wait → en=1 → wait → phydiag 268 dsc on both units → retimer serdes-tx-get / serdes-rx-get for sys 0..7. One log per run under ~/dsc_log/, split by ### TEST CYCLE n/N.
  • Waiting is a poll of bcmcmd ps 268, not show interfaces status. port en= changes the SDK, and the SONiC table only follows once gbsyncd has synced it — and this test pauses gbsyncd.
  • -d echoes every command as a grey [CMD] line before running it; -n is a dry run that touches nothing; the cycle count can be a bare argument (./bcm_100g_dsc_cycle.sh 200).

  🐛 Bug fixes

  blanton_ber.sh init reported a hard error on runs that were working

  • [ERR ] unit 1: the BCM shell rejected 'phydiag ... prbs get' — except the command was fine. prbs get prints one line per lane, a lane that has not locked says PRBS Error!, and the rejection check grepped the whole output case-insensitively for ERROR|Invalid|....
  • Worse than the false alarm: the function returned early, so the lock count that was meant to judge those very lanes never ran. The operator saw an error they could not act on, and did not see which lanes had failed to lock. That check has been there since v1.0.0.
  • Per-lane result lines are now excluded, the match is case-sensitive, and a genuine rejection prints the offending line.

  🔧 Changes

  • Script A takes a BER baseline before its first traffic run (v1.2.1), so together with Script C's closing sweep the pair brackets the soak.
  • EN_TX_FIR gates the SerDes DSC scans in Script A and Script C. Default 0: a full scan is ~10 min and both scripts do one.

  📦 Downloads

  File	Contents
  Script_ABC_Blanton_V1.2.2.zip	The full Tera Term working directory, including Blanton_Script/ to copy onto the DUT

  chmod +x ~/Blanton_Script/*.sh
  grep -rlU $'\r' ~/Blanton_Script    # expect no output
  ls ~/hammer/tools/amd/mlucas-avx2   # must already be there
  

  ⚠️ Before you run

  • Replace config.ttl with the macros. EN_Cold_Warm_boot is new, and Tera Term aborts on an undefined variable rather than treating it as 0.
  • Do not run the boot cycle with EN_Cold_Warm_boot = 0. Nothing reboots, the wait "Booting in blind mode" underneath has no timeout, and since v1.2.2 there is no logopen either — so it hangs and leaves no log showing where. 0 is the value for the A → B → C flow, where that macro is not used.
  • The cold path writes a raw FPGA register. 0x480 is ICB_CTRL_REG; the register map carries no bit definitions for it and 0xD0000 is not documented anywhere in this repo. The BDF 0000:05:00.0 is hard-coded while blanton_fpga_pcimem.sh auto-detects it because it moves per unit — check the BDF on every board before running the cold path.
  • Anything that parses these logs must accept both banners, Reboot Cycle : N and Power Cycle : N. A parser that greps only the first finds zero cycles in a power-cycle log and reports nothing without complaining.
  • bcm_100g_dsc_cycle.sh has not been run on hardware. It pauses gbsyncd0/1 for tuning and unpauses them on exit, Ctrl-C included; -P leaves them alone.
  • sleep 30 and BER_INTERVAL now live in three places — Script A, Script C and blanton_ber.sh.
  • BER, the DSC cycle, blanton_traffic_linespeed and blanton_tr518.sh cannot overlap. They all take the same ports.
  • Script 4 has no teardown: finish it with blanton_tr518.sh stop and systemctl stop mlucas-amm.
  • blanton_multiphase_margin.sh save is permanent, and must not be mixed with margin.sh.
  • READ_VIN and READ_IIN are still not in the ADPM12200 coefficient table.
  • FAN_SPEED is 100.

  🔗 Links

  • ARCHITECTURE.md — test flow, data models, constraints
  • CLAUDE.md — commands and the bench gotchas

  Full changelog: V1.2.1...V1.2.2

  Downloads

  • Script_ABC_Blanton_V1.2.2.zip
    221 KiB

    2026-09-15 21:27:50 +08:00
  • Source Code (ZIP)
  • Source Code (TAR.GZ)