Files

T

etwenandClaude Opus 5 24c704c667 docs(arch): Add ARCHITECTURE.md and CLAUDE.md, init repo

Bring the Blanton Tera Term TTL test suite under version control and
document how the pieces fit together.

- ARCHITECTURE.md: A/B/C script roles, host-to-DUT-to-FPGA data path,
  config/settings/profile data models, PCIe AER + EDAC topology table,
  10 key constraints, and 6 development phases derived from the
  Status_20260814 spreadsheet's On-Going items
- CLAUDE.md: stack, smoke-test commands, conventions, and the hardware
  footguns (per-unit BDF, VSPI vs VI2C timing, repeated START,
  STORE_USER_ALL, ARB_LOST false positives)
- secret/: gitignored credential store with README + .example template,
  so the DUT login stops living in 1_Blanton_Script_A.ttl
- .gitignore: secret/*, For_AI/, *.log, publish/, *.DSN

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_014RetWKFZFG1ZHcitQAyhwM

2026-08-17 08:52:11 +08:00

178 KiB

Raw Blame History

Blanton (Project Helios) FPGA Register Specification

Status: Draft · Source FPGA: CB / SWB / ICB Converted from Blantons_FPGA_Registers_draft.docx and Blantons_FPGA_Registers_Map_draft.xlsx. This Markdown is a faithful, human-readable rendering of the two HPE source files — values are not edited.

Revision History
Document Abbreviations
Register Address Map
MSI Interrupt Mapping
Register Descriptions

1. Revision History

Revision No.	Date mm/dd/yy	Author	Changes
0.1	03/20/2026	Peter	1st Draft
0.2	03/23/2026	Peter	Reviewed by HW
0.3	04/06/2026	Peter	CB F0 PWR_CTRL/STAT changes Move USRPRT power to F1 USRPRT_PWR_CTRL/STAT Move USB 5V to USB_CTRL_REG Added separate THRM_SUICIDE bit control for SWB 0/1 Added power status of SWB0/1 - #SWB_PWROK USB_STAT_REG – added new detection bit [1] ICB_CTRL_REG [3:0] – added encoded reset control to ICB Fix minor typo in F1 registers F1 USRPRT_PWR_CTRL – Efuse to QSFP are default to disabled TND_BMC_GPIO_CTRL/STAT/DIR – replace bit [7] with [0] Updated LED_CTRL_4/5_REG description Decouple SWB reset signal into RST_CAUSE_SWB_REG (from RST_CAUSE_REG) TND_PWR_CTRL/STAT_REG – added new power rails control and status bits F1 RTM_CTL_REG #RTM_RST default change to asserted

Register-map spreadsheet revisions:

Rev	Date	Description
0.1	2026-03-20	First Draft
0.2	2026-03-23	Reviewed by HW
0.3	2026-04-07	- Add missing INTRD_STAT_REG - Add USRPRT_PWR_CTRL/STAT_REG - Updated CB-MSI / SWB-INT / ICB-INT tabs - Added USB_CTRL_REG - Added RST_CAUSE_SWB_REG (SWB0/1)

2. Document Abbreviations

Abbr.	Meaning
TBD	To be determined
W1C	Write 1 to clear
W0C	Write 0 to clear
RO	Read Only
WO	Write Only
RW	Read & Write

3. Register Address Map

Address map of every FPGA register, grouped by FPGA type and PCI function. Offsets are byte offsets within the function register window. DW = number of 32-bit double-words the entry occupies.

CB — Control Board

CB — Function 0

Offset	DW	Register	Group	Comment
0x000	1	FPGA_REV_ID_REG	GEN & ID	CB_FPGA revision & Id register
0x004	1	RSVD	GEN & ID
0x008	1	RSVD	GEN & ID
0x00C	1	RSVD	GEN & ID
0x010	12	RSVD	GEN & ID
0x040	1	FUNC_CAP_0_REG	GEN & ID
0x044	1	FUNC_CAP_1_REG	GEN & ID
0x048	1	FUNC_CAP_2_REG	GEN & ID
0x04C	1	FUNC_CAP_3_REG	GEN & ID
0x050	1	FUNC_CAP_4_REG	GEN & ID
0x054	1	FUNC_CAP_5_REG	GEN & ID
0x058	1	FUNC_CAP_6_REG	GEN & ID
0x05C	1	FUNC_CAP_7_REG	GEN & ID
0x060	1	FUNC_CAP_8_REG	GEN & ID
0x064	7	RSVD	GEN & ID
0x080	1	FPGA_RECONFIG_CTRL_REG	FPGA Reconfig
0x084	1	FPGA_RECONFIG_STAT_REG	FPGA Reconfig
0x088	6	RSVD	FPGA Reconfig	88
0x0A0	1	RSVD	FPGA Reconfig
0x0A4	1	RSVD	FPGA Reconfig
0x0A8	6	RSVD	FPGA Reconfig
0x0C0	1	SCRTCH_0_REG	Scratchpad
0x0C4	1	SCRTCH_1_REG	Scratchpad
0x0C8	1	SCRTCH_2_REG	Scratchpad
0x0CC	1	SCRTCH_3_REG	Scratchpad
0x0D0	12	RSVD	Scratchpad
0x100	1	DEV_MSI_0_PEND_REG	MSI INT
0x104	1	RSVD	MSI INT
0x108	1	DEV_MSI_0_INT_EN_REG	MSI INT
0x10C	1	RSVD	MSI INT
0x110	1	DEV_MSI_1_PEND_REG	MSI INT
0x114	1	RSVD	MSI INT
0x118	1	DEV_MSI_1_INT_EN_REG	MSI INT
0x11C	1	RSVD	MSI INT
0x120	1	DEV_MSI_2_PEND_REG	MSI INT
0x124	1	RSVD	MSI INT
0x128	1	DEV_MSI_2_INT_EN_REG	MSI INT
0x12C	1	RSVD	MSI INT
0x130	1	DEV_MSI_3_PEND_REG	MSI INT
0x134	1	RSVD	MSI INT
0x138	1	DEV_MSI_3_INT_EN_REG	MSI INT
0x13C	1	RSVD	MSI INT
0x140	1	DEV_MSI_4_PEND_REG	MSI INT
0x144	1	RSVD	MSI INT
0x148	1	DEV_MSI_4_INT_EN_REG	MSI INT
0x14C	1	RSVD	MSI INT
0x150	1	DEV_MSI_5_PEND_REG	MSI INT
0x154	1	RSVD	MSI INT
0x158	1	DEV_MSI_5_INT_EN_REG	MSI INT
0x15C	1	RSVD	MSI INT
0x160	1	DEV_MSI_6_PEND_REG	MSI INT	160
0x164	1	RSVD	MSI INT
0x168	1	DEV_MSI_6_INT_EN_REG	MSI INT
0x16C	1	RSVD	MSI INT
0x170	1	DEV_MSI_7_PEND_REG	MSI INT
0x174	1	RSVD	MSI INT
0x178	1	DEV_MSI_7_INT_EN_REG	MSI INT
0x17C	1	RSVD	MSI INT
0x180	64	RSVD	MSI INT
0x280	32	RSVD	Mailbox
0x300	1	PWR_CTRL_REG	Power
0x304	1	PWR_STAT_REG	Power
0x308	1	PWR_STAT_PLRTY_REG	Power
0x30C	1	PWR_STAT_EDG_LVL_REG	Power
0x310	1	PWR_STAT_INT_EN_REG	Power
0x314	1	PWR_STAT_INT_STAT_REG	Power
0x318	1	PWR_STAT_INT_CLR_REG	Power
0x31C	1	SEM_REG	Power
0x320	24	RSVD	Power
0x380	1	RS232_SPD_SNS_REG	Speed Sense
0x384	1	RS232_CLR_SPD_SNS_REG	Speed Sense
0x388	14	RSVD	Speed Sense
0x3C0	1	RSVD	TPM	For TPM 1.0 and 2.0
0x3C4	1	TPM_STAT_REG	TPM
0x3C8	1	TPM_STAT_PLRTY_REG	TPM
0x3CC	1	TPM_STAT_EDG_LVL_REG	TPM
0x3D0	1	TPM_STAT_INT_EN_REG	TPM
0x3D4	1	TPM_STAT_INT_STAT_REG	TPM
0x3D8	1	TPM_STAT_INT_CLR_REG	TPM
0x3DC	1	SEM_REG	TPM
0x3E0	24	RSVD	TPM
0x440	1	PMC_CTRL_REG	PMC
0x444	1	PMC_STAT_REG	PMC
0x448	1	PMC_STAT_PLRTY_REG	PMC
0x44C	1	PMC_STAT_EDG_LVL_REG	PMC
0x450	1	PMC_STAT_INT_EN_REG	PMC
0x454	1	PMC_STAT_INT_STAT_REG	PMC
0x458	1	PMC_STAT_INT_CLR_REG	PMC
0x45C	1	SEM_REG	PMC
0x460	8	RSVD	PMC
0x480	1	ICB_CTRL_REG	ICB
0x484	1	ICB_STAT_REG	ICB
0x488	1	ICB_STAT_PLRTY_REG	ICB
0x48C	1	ICB_STAT_EDG_LVL_REG	ICB
0x490	1	ICB_STAT_INT_EN_REG	ICB
0x494	1	ICB_STAT_INT_STAT_REG	ICB
0x498	1	ICB_STAT_INT_CLR_REG	ICB
0x49C	1	SEM_REG	ICB
0x4A0	8	RSVD	ICB
0x4C0	1	SWB_CTRL_REG	SWB0
0x4C4	1	SWB_STAT_REG	SWB0
0x4C8	1	SWB_STAT_PLRTY_REG	SWB0
0x4CC	1	SWB_STAT_EDG_LVL_REG	SWB0
0x4D0	1	SWB_STAT_INT_EN_REG	SWB0
0x4D4	1	SWB_STAT_INT_STAT_REG	SWB0
0x4D8	1	SWB_STAT_INT_CLR_REG	SWB0
0x4DC	1	SEM_REG	SWB0
0x4E0	8	RSVD	SWB0
0x500	1	SWB_CTRL_REG	SWB1
0x504	1	SWB_STAT_REG	SWB1	504
0x508	1	SWB_STAT_PLRTY_REG	SWB1
0x50C	1	SWB_STAT_EDG_LVL_REG	SWB1
0x510	1	SWB_STAT_INT_EN_REG	SWB1
0x514	1	SWB_STAT_INT_STAT_REG	SWB1
0x518	1	SWB_STAT_INT_CLR_REG	SWB1
0x51C	1	SEM_REG	SWB1
0x520	8	RSVD	SWB1
0x540	1	BMC_CTRL_REG	BMC
0x544	1	BMC_STAT_REG	BMC
0x548	1	BMC_STAT_PLRTY_REG	BMC
0x54C	1	BMC_STAT_EDG_LVL_REG	BMC
0x550	1	BMC_STAT_INT_EN_REG	BMC
0x554	1	BMC_STAT_INT_STAT_REG	BMC
0x558	1	BMC_STAT_INT_CLR_REG	BMC
0x55C	1	SEM_REG	BMC
0x560	8	RSVD	BMC
0x580	1	RSVD	THRM
0x584	1	THRM_STAT_REG	THRM
0x588	1	THRM_STAT_PLRTY_REG	THRM
0x58C	1	THRM_STAT_EDG_LVL_REG	THRM
0x590	1	THRM_STAT_INT_EN_REG	THRM
0x594	1	THRM_STAT_INT_STAT_REG	THRM
0x598	1	THRM_STAT_INT_CLR_REG	THRM
0x59C	1	SEM_REG	THRM
0x5A0	8	RSVD	THRM
0x5C0	1	USB_CTRL_REG	USB
0x5C4	1	USB_STAT_REG	USB
0x5C8	1	USB_STAT_PLRTY_REG	USB
0x5CC	1	USB_STAT_EDG_LVL_REG	USB
0x5D0	1	USB_STAT_INT_EN_REG	USB
0x5D4	1	USB_STAT_INT_STAT_REG	USB
0x5D8	1	USB_STAT_INT_CLR_REG	USB
0x5DC	1	SEM_REG	USB
0x5E0	8	RSVD	USB
0x600	1	RSVD	BTN
0x604	1	BTN_STAT_REG	BTN
0x608	1	BTN_STAT_PLRTY_REG	BTN
0x60C	1	BTN_STAT_EDG_LVL_REG	BTN
0x610	1	BTN_STAT_INT_EN_REG	BTN
0x614	1	BTN_STAT_INT_STAT_REG	BTN
0x618	1	BTN_STAT_INT_CLR_REG	BTN
0x61C	1	SEM_REG	BTN
0x620	8	RSVD	BTN
0x640	1	RSVD	LEAK
0x644	1	LEAK_STAT_REG	LEAK
0x648	1	LEAK_STAT_PLRTY_REG	LEAK	648
0x64C	1	LEAK_STAT_EDG_LVL_REG	LEAK
0x650	1	LEAK_STAT_INT_EN_REG	LEAK	650
0x654	1	LEAK_STAT_INT_STAT_REG	LEAK
0x658	1	LEAK_STAT_INT_CLR_REG	LEAK
0x65C	1	SEM_REG	LEAK
0x660	8	RSVD	LEAK
0x680	1	NFC_CTRL_REG	NFC
0x684	1	NFC_STAT_REG	NFC
0x688	1	NFC_STAT_PLRTY_REG	NFC
0x68C	1	NFC_STAT_EDG_LVL_REG	NFC
0x690	1	NFC_STAT_INT_EN_REG	NFC
0x694	1	NFC_STAT_INT_STAT_REG	NFC
0x698	1	NFC_STAT_INT_CLR_REG	NFC
0x69C	1	SEM_REG	NFC
0x6A0	8	RSVD	NFC
0x6C0	1	RSVD	Intrusion
0x6C4	1	INTRD_STAT_REG	Intrusion
0x6C8	1	INTRD_STAT_PLRTY_REG	Intrusion
0x6CC	1	INTRD_STAT_EDG_LVL_REG	Intrusion
0x6D0	1	INTRD_STAT_INT_EN_REG	Intrusion
0x6D4	1	INTRD_STAT_INT_STAT_REG	Intrusion
0x6D8	1	INTRD_STAT_INT_CLR_REG	Intrusion
0x6DC	1	SEM_REG	Intrusion
0x6E0	8	RSVD	Intrusion
0x700	1	RSVD	Battery
0x704	1	BTRY_STAT_REG	Battery
0x708	1	BTRY_STAT_PLRTY_REG	Battery
0x70C	1	BTRY_STAT_EDG_LVL_REG	Battery
0x710	1	BTRY_STAT_INT_EN_REG	Battery
0x714	1	BTRY_STAT_INT_STAT_REG	Battery
0x718	1	BTRY_STAT_INT_CLR_REG	Battery
0x71C	1	SEM_REG	Battery
0x720	8	RSVD	Battery
0x740	32	RSVD	RSVD
0x7C0	1	RSVD	Other Dev ctrl-stat-int
0x7C4	1	RSVD	Other Dev ctrl-stat-int
0x7C8	1	RSVD	Other Dev ctrl-stat-int
0x7CC	1	EN_ACCSS_PRTCTD_REG	Other Dev ctrl-stat-int
0x7D0	1	UART_MUX_REG	Other Dev ctrl-stat-int
0x7D4	1	I2C_MUX_RST_REG	Other Dev ctrl-stat-int
0x7D8	1	CPU_INTR_CTRL_REG	Other Dev ctrl-stat-int
0x7DC	1	BMC_JTAG_CTRL_REG	Other Dev ctrl-stat-int
0x7E0	1	SWB0_JTAG_CTRL_REG	Other Dev ctrl-stat-int
0x7E4	1	SWB1_JTAG_CTRL_REG	Other Dev ctrl-stat-int
0x7E8	198	RSVD	RSVD
0xB00	1	FLSH_CTRL_REG	Flash Write Protect
0xB04	31	RSVD	Flash Write Protect
0xB80	1	LED_SYNC_REG	LED
0xB84	1	LED_CONFIG_REG	LED
0xB88	1	LED_CTRL_0_REG	LED
0xB8C	1	LED_CTRL_1_REG	LED
0xB90	1	LED_CTRL_2_REG	LED
0xB94	1	LED_CTRL_3_REG	LED
0xB98	1	LED_CTRL_4_REG	LED
0xB9C	1	LED_CTRL_5_REG	LED
0xBA0	1	RSVD	LED
0xBA4	1	RSVD	LED
0xBA8	1	RSVD	LED
0xBAC	1	RSVD	LED
0xBB0	1	RSVD	LED
0xBB4	8	RSVD	RSVD
0xBD4	1	WDG_CTRL_REG	WDG Ctrl-Stat-int
0xBD8	1	WDG_STAT_REG	WDG Ctrl-Stat-int
0xBDC	1	WDG_RST_REG	WDG Ctrl-Stat-int
0xBE0	8	RSVD	RSVD
0xC00	1	TND_CTRL_REG	Debug & Test
0xC04	1	TND_STAT_REG	Debug & Test
0xC08	1	TND_PWR_CTRL_REG	Debug & Test
0xC0C	1	TND_PWR_STAT_REG	Debug & Test
0xC10	1	TND_CLK_CTRL_REG	Debug & Test
0xC14	1	RSVD	Debug & Test
0xC18	1	TND_PMC_GPIO_CTRL_REG	Debug & Test
0xC1C	1	TND_PMC_GPIO_STAT_REG	Debug & Test
0xC20	1	TND_PMC_GPIO_DIR_CTRL_REG	Debug & Test
0xC24	1	TND_BMC_GPIO_CTRL_REG	Debug & Test
0xC28	1	TND_BMC_GPIO_STAT_REG	Debug & Test
0xC2C	1	TND_BMC_GPIO_DIR_CTRL_REG	Debug & Test
0xC30	1	TND_SWB0_GPIO_CTRL_REG	Debug & Test
0xC34	1	TND_SWB0_GPIO_STAT_REG	Debug & Test
0xC38	1	TND_SWB0_GPIO_DIR_CTRL_REG	Debug & Test
0xC3C	1	TND_SWB1_GPIO_CTRL_REG	Debug & Test
0xC40	1	TND_SWB1_GPIO_STAT_REG	Debug & Test
0xC44	1	TND_SWB1_GPIO_DIR_CTRL_REG	Debug & Test
0xC48	1	TND_ICB_GPIO_DIR_CTRL_REG	Debug & Test
0xC4C	1	TND_ICB_GPIO_DIR_CTRL_REG	Debug & Test
0xC50	1	TND_ICB_GPIO_DIR_CTRL_REG	Debug & Test
0xC54	79	RSVD	Debug & Test
0xD90	1	RST_CAUSE_REG	Reset Stat
0xD94	1	RST_CAUSE_SWB_REG	Reset Stat SWB0	For SWB 0
0xD98	1	RST_CAUSE_SWB_REG	Reset Stat SWB1	For SWB 1
0xD9C	1	RSVD	RSVD

CB — Function 1

Offset	DW	Register	Group	Comment
0x000	1	FPGA_REV_ID_REG	GEN & ID	MCB FPGA revision & Id register
0x004	1	RSVD	GEN & ID
0x008	1	RSVD	GEN & ID
0x00C	13	RSVD	GEN & ID
0x040	1	FUNC_CAP_0_REG	GEN & ID	number of interrupts for MSI vectors 0 to 3
0x044	1	FUNC_CAP_1_REG	GEN & ID	number of interrupts for MSI vectors 4 to 7
0x048	1	FUNC_CAP_2_REG	GEN & ID	number of interrupts for MSI vectors 8 to 11
0x04C	1	FUNC_CAP_3_REG	GEN & ID	number of interrupts for MSI vectors 12 to 15
0x050	1	FUNC_CAP_4_REG	GEN & ID	number of interrupts for MSI vectors 16 to 19
0x054	1	FUNC_CAP_5_REG	GEN & ID	number of interrupts for MSI vectors 20 to 23
0x058	1	FUNC_CAP_6_REG	GEN & ID	number of interrupts for MSI vectors 24 to 27
0x05C	1	FUNC_CAP_7_REG	GEN & ID	number of interrupts for MSI vectors 28 to 31
0x060	1	FUNC_CAP_8_REG	GEN & ID
0x064	7	RSVD	GEN & ID
0x080	16	RSVD	RSVD
0x0C0	1	SCRTCH_0_REG	Scratchpad	Scratch Registers for SW use
0x0C4	1	SCRTCH_1_REG	Scratchpad	Scratch Registers for SW use
0x0C8	1	SCRTCH_2_REG	Scratchpad	Scratch Registers for SW use
0x0CC	1	SCRTCH_3_REG	Scratchpad	Scratch Registers for SW use
0x0D0	12	RSVD	Scratchpad	12 register reserved for scratch
0x100	1	DEV_MSI_0_PEND_REG	MSI INT
0x104	1	RSVD	MSI INT	to extend DEV_MSI_PEND_REG
0x108	1	DEV_MSI_0_INT_EN_REG	MSI INT
0x10C	1	RSVD	RSVD	to extend DEV_MSI_INT_EN_REG
0x110	1	DEV_MSI_1_PEND_REG	MSI INT	For other MSI Ctrl registers or INT vector registers
0x114	1	RSVD	MSI INT
0x118	1	DEV_MSI_1_INT_EN_REG	MSI INT
0x11C	1	RSVD	RSVD
0x120	1	DEV_MSI_2_PEND_REG	MSI INT
0x124	1	RSVD	MSI INT
0x128	1	DEV_MSI_2_INT_EN_REG	MSI INT
0x12C	1	RSVD	MSI INT
0x130	1	DEV_MSI_3_PEND_REG	MSI INT
0x134	1	RSVD	MSI INT
0x138	1	DEV_MSI_3_INT_EN_REG	MSI INT
0x13C	1	RSVD	MSI INT
0x140	1	DEV_MSI_4_PEND_REG	MSI INT
0x144	1	RSVD	MSI INT
0x148	1	DEV_MSI_4_INT_EN_REG	MSI INT
0x14C	1	RSVD	MSI INT
0x150	1	DEV_MSI_5_PEND_REG	MSI INT
0x154	1	RSVD	MSI INT
0x158	1	DEV_MSI_5_INT_EN_REG	MSI INT
0x15C	1	RSVD	MSI INT
0x160	1	DEV_MSI_6_PEND_REG	MSI INT
0x164	1	RSVD	MSI INT
0x168	1	DEV_MSI_6_INT_EN_REG	MSI INT
0x16C	117	RSVD	RSVD
0x340	1	FAN_CTRL_REG	FAN
0x344	1	FAN_STAT_REG	FAN
0x348	1	FAN_STAT_PLRTY_REG	FAN
0x34C	1	FAN_STAT_EDG_LVL_REG	FAN
0x350	1	FAN_STAT_INT_EN_REG	FAN	350
0x354	1	FAN_STAT_INT_STAT_REG	FAN
0x358	1	FAN_STAT_INT_CLR_REG	FAN
0x35C	1	SEM_REG	FAN
0x360	8	RSVD	RSVD
0x380	1	RTM_CTRL_REG	Retimer
0x384	1	RTM_STAT_REG	Retimer
0x388	1	RTM_STAT_PLRTY_REG	Retimer
0x38C	1	RTM_STAT_EDG_LVL_REG	Retimer
0x390	1	RTM_STAT_INT_EN_REG	Retimer
0x394	1	RTM_STAT_INT_STAT_REG	Retimer
0x398	1	RTM_STAT_INT_CLR_REG	Retimer
0x39C	1	SEM_REG	Retimer
0x3A0	8	RSVD	Retimer
0x3C0	1	ETH_CTRLR_CTRL_REG	Ethernet Controller
0x3C4	1	ETH_CTRLR_STAT_REG	Ethernet Controller	3C4
0x3C8	1	ETH_CTRLR_STAT_PLRTY_REG	Ethernet Controller
0x3CC	1	ETH_CTRLR_STAT_EDG_LVL_REG	Ethernet Controller
0x3D0	1	ETH_CTRLR_STAT_INT_EN_REG	Ethernet Controller
0x3D4	1	ETH_CTRLR_STAT_INT_STAT_REG	Ethernet Controller
0x3D8	1	ETH_CTRLR_STAT_INT_CLR_REG	Ethernet Controller
0x3DC	1	SEM_REG	Ethernet Controller
0x3E0	8	RSVD	Ethernet Controller
0x400	240	RSVD	RSVD
0x7C0	1	USRPRT_PWR_CTRL_REG	FE Power stat-ctrl
0x7C4	1	USRPRT_PWR_STAT_REG	FE Power stat-ctrl
0x7C8	1	USRPRT_PWR_STAT_PLRTY_REG	FE Power stat-ctrl
0x7CC	1	USRPRT_PWR_STAT_EDG_LVL_REG	FE Power stat-ctrl
0x7D0	1	USRPRT_PWR_STAT_INT_EN_REG	FE Power stat-ctrl
0x7D4	1	USRPRT_PWR_STAT_INT_STAT_REG	FE Power stat-ctrl
0x7D8	1	USRPRT_PWR_STAT_INT_CLR_REG	FE Power stat-ctrl
0x7DC	1	SEM_REG	FE Power stat-ctrl
0x7E0	8	RSVD	FE Power stat-ctrl
0x800	1	USRPRT_CTRL_0_REG	FE stat-ctrl
0x804	1	USRPRT_STAT_0_REG	FE stat-ctrl
0x808	1	USRPRT_STAT_0_PLRTY_REG	FE stat-ctrl
0x80C	1	USRPRT_STAT_0_EDG_LVL_REG	FE stat-ctrl
0x810	1	USRPRT_STAT_0_INT_EN_REG	FE stat-ctrl
0x814	1	USRPRT_STAT_0_INT_STAT_REG	FE stat-ctrl
0x818	1	USRPRT_STAT_0_INT_CLR_REG	FE stat-ctrl
0x81C	1	SEM_REG	FE stat-ctrl
0x820	8	RSVD	FE stat-ctrl
0x840	1	USRPRT_CTRL_1_REG	FE stat-ctrl
0x844	1	USRPRT_STAT_1_REG	FE stat-ctrl
0x848	1	USRPRT_STAT_1_PLRTY_REG	FE stat-ctrl
0x84C	1	USRPRT_STAT_1_EDG_LVL_REG	FE stat-ctrl
0x850	1	USRPRT_STAT_1_INT_EN_REG	FE stat-ctrl
0x854	1	USRPRT_STAT_1_INT_STAT_REG	FE stat-ctrl
0x858	1	USRPRT_STAT_1_INT_CLR_REG	FE stat-ctrl
0x85C	1	SEM_REG	FE stat-ctrl
0x860	8	RSVD	FE stat-ctrl
0x880	96	RSVD	RSVD
0xA00	1	PHY_CTRL_0_REG	PHY stat-ctrl
0xA04	1	RSVD	PHY stat-ctrl
0xA08	1	RSVD	PHY stat-ctrl
0xA0C	1	RSVD	PHY stat-ctrl
0xA10	1	RSVD	PHY stat-ctrl
0xA14	1	RSVD	PHY stat-ctrl
0xA18	1	RSVD	PHY stat-ctrl
0xA1C	1	RSVD	PHY stat-ctrl
0xA20	8	RSVD	PHY stat-ctrl
0xA40	16	RSVD	RSVD

CB — Function 2

Offset	DW	Register	Group	Comment
0x000	1	FPGA_REV_ID_REG	GEN & ID	MCB FPGA revision & Id register
0x004	1	RSVD	GEN & ID
0x008	1	RSVD	GEN & ID
0x00C	13	RSVD	GEN & ID
0x040	1	FUNC_CAP_0_REG	GEN & ID	number of interrupts for MSI vectors 0 to 3
0x044	1	FUNC_CAP_1_REG	GEN & ID	number of interrupts for MSI vectors 4 to 7
0x048	1	FUNC_CAP_2_REG	GEN & ID	number of interrupts for MSI vectors 8 to 11
0x04C	1	FUNC_CAP_3_REG	GEN & ID	number of interrupts for MSI vectors 12 to 15
0x050	1	FUNC_CAP_4_REG	GEN & ID	number of interrupts for MSI vectors 16 to 19
0x054	1	FUNC_CAP_5_REG	GEN & ID	number of interrupts for MSI vectors 20 to 23
0x058	1	FUNC_CAP_6_REG	GEN & ID	number of interrupts for MSI vectors 24 to 27
0x05C	1	FUNC_CAP_7_REG	GEN & ID	number of interrupts for MSI vectors 28 to 31
0x060	1	FUNC_CAP_8_REG	GEN & ID
0x064	7	RSVD	GEN & ID
0x080	16	RSVD	RSVD
0x0C0	1	SCRTCH_0_REG	Scratchpad	Scratch Registers for SW use
0x0C4	1	SCRTCH_1_REG	Scratchpad	Scratch Registers for SW use
0x0C8	1	SCRTCH_2_REG	Scratchpad	Scratch Registers for SW use
0x0CC	1	SCRTCH_3_REG	Scratchpad	Scratch Registers for SW use
0x0D0	12	RSVD	Scratchpad	12 register reserved for scratch
0x100	1	DEV_MSI_0_PEND_REG	MSI INT
0x104	1	RSVD	MSI INT	to extend DEV_MSI_PEND_REG
0x108	1	DEV_MSI_0_INT_EN_REG	MSI INT
0x10C	1	RSVD	MSI INT	to extend DEV_MSI_INT_EN_REG
0x110	124	RSVD	MSI INT	For other MSI Ctrl registers or INT vector registers
0x300	1	SPI_CMD_STAT_REG	SPI-flash	Ready, NEW_CMD, Read, Write, Erase, Read Silicon Id, Illegal Erase, Illegal Write
0x304	1	SPI_ADD_REG	SPI-flash	Word address
0x308	1	SPI_WR_DATA_REG	SPI-flash	32-bit data to be written in Configuration Flash Memory
0x30C	1	SPI_RD_DATA_REG	SPI-flash	Holds read data form configuration Flash memory.
0x310	1	SPI_RST_REG	SPI-flash	Reset FPGA SPI module.
0x314	1	SEM_REG	SPI-flash	Semaphore Register
0x318	10	RSVD	RSVD
0x340	1	SPI_CMD_STAT_REG	VSPI-Flash-PMC	Ready, NEW_CMD, Read, Write, Erase, Read Silicon Id, Illegal Erase, Illegal Write
0x344	1	SPI_ADD_REG	VSPI-Flash-PMC	Word address
0x348	1	SPI_WR_DATA_REG	VSPI-Flash-PMC	32-bit data to be written in Configuration Flash Memory
0x34C	1	SPI_RD_DATA_REG	VSPI-Flash-PMC	Holds read data form configuration Flash memory.
0x350	1	SPI_RST_REG	VSPI-Flash-PMC	Reset VSPI-Flash module.
0x354	11	RSVD	RSVD
0x380	1	SPI_CMD_STAT_REG	VSPI-Flash-ICB	Ready, NEW_CMD, Read, Write, Erase, Read Silicon Id, Illegal Erase, Illegal Write
0x384	1	SPI_ADD_REG	VSPI-Flash-ICB	Word address
0x388	1	SPI_WR_DATA_REG	VSPI-Flash-ICB	32-bit data to be written in Configuration Flash Memory
0x38C	1	SPI_RD_DATA_REG	VSPI-Flash-ICB	Holds read data form configuration Flash memory.
0x390	1	SPI_RST_REG	VSPI-Flash-ICB	Reset VSPI-Flash module.
0x394	11	RSVD	RSVD
0x3C0	1	SPI_CMD_STAT_REG	VSPI-Flash-SWB0	Ready, NEW_CMD, Read, Write, Erase, Read Silicon Id, Illegal Erase, Illegal Write
0x3C4	1	SPI_ADD_REG	VSPI-Flash-SWB0	Word address
0x3C8	1	SPI_WR_DATA_REG	VSPI-Flash-SWB0	32-bit data to be written in Configuration Flash Memory
0x3CC	1	SPI_RD_DATA_REG	VSPI-Flash-SWB0	Holds read data form configuration Flash memory.
0x3D0	1	SPI_RST_REG	VSPI-Flash-SWB0	Reset VSPI-Flash module.
0x3D4	11	RSVD	RSVD
0x400	1	SPI_CMD_STAT_REG	VSPI-Flash-SWB1	Ready, NEW_CMD, Read, Write, Erase, Read Silicon Id, Illegal Erase, Illegal Write
0x404	1	SPI_ADD_REG	VSPI-Flash-SWB1	Word address
0x408	1	SPI_WR_DATA_REG	VSPI-Flash-SWB1	32-bit data to be written in Configuration Flash Memory
0x40C	1	SPI_RD_DATA_REG	VSPI-Flash-SWB1	Holds read data form configuration Flash memory.
0x410	1	SPI_RST_REG	VSPI-Flash-SWB1	Reset VSPI-Flash module.
0x414	11	RSVD	RSVD
0x440	128	RSVD	RSVD	Reserved space for more VSPI-Flash channels
0x640	1	SPI_CMD_STAT_REG	VSPI-PMC	Ready, NEW_CMD, Read, Write, Erase, Read Silicon Id, Illegal Erase, Illegal Write
0x644	1	SPI_ADD_REG	VSPI-PMC	Word address
0x648	1	SPI_WR_DATA_REG	VSPI-PMC	32-bit data to be written in Configuration Flash Memory
0x64C	1	SPI_RD_DATA_REG	VSPI-PMC	Holds read data form configuration Flash memory.
0x650	1	SPI_RST_REG	VSPI-PMC	Reset VSPI module.
0x654	11	RSVD	RSVD
0x680	1	SPI_CMD_STAT_REG	VSPI-ICB	Ready, NEW_CMD, Read, Write, Erase, Read Silicon Id, Illegal Erase, Illegal Write
0x684	1	SPI_ADD_REG	VSPI-ICB	Word address
0x688	1	SPI_WR_DATA_REG	VSPI-ICB	32-bit data to be written in Configuration Flash Memory
0x68C	1	SPI_RD_DATA_REG	VSPI-ICB	Holds read data form configuration Flash memory.
0x690	1	SPI_RST_REG	VSPI-ICB	Reset VSPI module.
0x694	11	RSVD	RSVD
0x6C0	1	SPI_CMD_STAT_REG	VSPI-SWB0	Ready, NEW_CMD, Read, Write, Erase, Read Silicon Id, Illegal Erase, Illegal Write
0x6C4	1	SPI_ADD_REG	VSPI-SWB0	Word address
0x6C8	1	SPI_WR_DATA_REG	VSPI-SWB0	32-bit data to be written in Configuration Flash Memory
0x6CC	1	SPI_RD_DATA_REG	VSPI-SWB0	Holds read data form configuration Flash memory.
0x6D0	1	SPI_RST_REG	VSPI-SWB0	Reset VSPI module.
0x6D4	11	RSVD	RSVD
0x700	1	SPI_CMD_STAT_REG	VSPI-SWB1	Ready, NEW_CMD, Read, Write, Erase, Read Silicon Id, Illegal Erase, Illegal Write
0x704	1	SPI_ADD_REG	VSPI-SWB1	Word address
0x708	1	SPI_WR_DATA_REG	VSPI-SWB1	32-bit data to be written in Configuration Flash Memory
0x70C	1	SPI_RD_DATA_REG	VSPI-SWB1	Holds read data form configuration Flash memory.
0x710	1	SPI_RST_REG	VSPI-SWB1	Reset VSPI module.
0x714	11	RSVD	RSVD
0x740	64	RSVD	RSVD	Reserved space for more VSPI channels
0x840	1	GEN_SPI_RD_DATA_REG	GEN-SPI-SWB0	Generic SPI interface to SWB0, alternate route TH6 SPI flash
0x844	1	GEN_SPI_WR_DATA_REG	GEN-SPI-SWB0
0x848	1	GEN_SPI_STAT_REG	GEN-SPI-SWB0
0x84C	1	GEN_SPI_CTRL_REG	GEN-SPI-SWB0
0x850	1	GEN_SPI_CFG_CTRL_REG	GEN-SPI-SWB0
0x854	1	GEN_SPI_SLV_REG	GEN-SPI-SWB0
0x858	1	SPI_RST_REG	GEN-SPI-SWB0
0x85C	1	SEM_REG	GEN-SPI-SWB0
0x860	8	RSVD	GEN-SPI-SWB0
0x880	1	GEN_SPI_RD_DATA_REG	GEN-SPI-SWB1	Generic SPI interface to SWB1, alternate route TH6 SPI flash
0x884	1	GEN_SPI_WR_DATA_REG	GEN-SPI-SWB1
0x888	1	GEN_SPI_STAT_REG	GEN-SPI-SWB1
0x88C	1	GEN_SPI_CTRL_REG	GEN-SPI-SWB1
0x890	1	GEN_SPI_CFG_CTRL_REG	GEN-SPI-SWB1
0x894	1	GEN_SPI_SLV_REG	GEN-SPI-SWB1
0x898	1	SPI_RST_REG	GEN-SPI-SWB1
0x89C	1	SEM_REG	GEN-SPI-SWB1
0x8A0	8	RSVD	GEN-SPI-SWB1
0x8C0	64	RSVD	RSVD	Reserved space for more SPI channels
0x9C0	1	MDIO_STAT_CMD_REG	MDIO-CH0	To Retimer
0x9C4	1	MDIO_CTRL_REG	MDIO-CH0
0x9C8	1	MDIO_STK_CTRL_REG	MDIO-CH0
0x9CC	1	MDIO_STK_ADDR_CONF_REG	MDIO-CH0
0x9D0	1	MDIO_STK_STAT_REG	MDIO-CH0
0x9D4	1	MDIO_STK_RAM_DATA_REG	MDIO-CH0
0x9D8	1	MDIO_STK_RAM_ADDR_REG	MDIO-CH0
0x9DC	1	MDIO_STAT_INT_REG	MDIO-CH0
0x9E0	128	RSVD	RSVD

CB — Function 3

Offset	DW	Register	Group	Comment
0x000	1	FPGA_REV_ID_REG	GEN & ID	MCB FPGA revision & Id register
0x004	1	RSVD	GEN & ID
0x008	1	RSVD	GEN & ID
0x00C	13	RSVD	GEN & ID
0x040	1	FUNC_CAP_0_REG	GEN & ID	number of interrupts for MSI vectors 0 to 3
0x044	1	FUNC_CAP_1_REG	GEN & ID	number of interrupts for MSI vectors 4 to 7
0x048	1	FUNC_CAP_2_REG	GEN & ID	number of interrupts for MSI vectors 8 to 11
0x04C	1	FUNC_CAP_3_REG	GEN & ID	number of interrupts for MSI vectors 12 to 15
0x050	1	FUNC_CAP_4_REG	GEN & ID	number of interrupts for MSI vectors 16 to 19
0x054	1	FUNC_CAP_5_REG	GEN & ID	number of interrupts for MSI vectors 20 to 23
0x058	1	FUNC_CAP_6_REG	GEN & ID	number of interrupts for MSI vectors 24 to 27
0x05C	1	FUNC_CAP_7_REG	GEN & ID	number of interrupts for MSI vectors 28 to 31
0x060	1	FUNC_CAP_8_REG	GEN & ID
0x064	7	RSVD	GEN & ID
0x080	16	RSVD	RSVD
0x0C0	1	SCRTCH_0_REG	Scratchpad	Scratch Registers for SW use
0x0C4	1	SCRTCH_1_REG	Scratchpad	Scratch Registers for SW use
0x0C8	1	SCRTCH_2_REG	Scratchpad	Scratch Registers for SW use
0x0CC	1	SCRTCH_3_REG	Scratchpad	Scratch Registers for SW use
0x0D0	12	RSVD	Scratchpad	12 register reserved for scratch
0x100	1	DEV_MSI_0_PEND_REG	MSI INT
0x104	1	RSVD	MSI INT	to extend DEV_MSI_PEND_REG
0x108	1	DEV_MSI_0_INT_EN_REG	MSI INT
0x10C	1	RSVD	MSI INT	to extend DEV_MSI_INT_EN_REG
0x110	124	RSVD	MSI INT	For other MSI Ctrl registers or INT vector registers
0x300	1	I2C_PRSCL_LO_REG	I2C-Ch0	SWB_0 1) M0 - 4ch I2C MUX TCA9546 (0xE8/0xE9) 2) M0.C0 Temp Sensor TPM432 (0x98/0x99) 3) M0.C1 Temp Sensor TPM432 (0x98/0x99) 4) M0.C2 Temp Sensor TPM432 (0x98/0x99)
0x304	1	I2C_PRSCL_HI_REG	I2C-Ch0
0x308	1	I2C_CTRL_REG	I2C-Ch0
0x30C	0	I2C_TX_REG	I2C-Ch0
0x30C	1	I2C_RX_REG	I2C-Ch0
0x310	0	I2C_CMD_REG	I2C-Ch0
0x310	1	I2C_STAT_REG	I2C-Ch0
0x314	1	I2C_MUX_SEL_REG	I2C-Ch0
0x318	1	I2C_RST_REG	I2C-Ch0
0x31C	1	SEM_REG	I2C-Ch0
0x320	1	I2C_PRSCL_LO_REG	I2C-Ch1	SWB_1 1) M0 - 4ch I2C MUX TCA9546 (0xE8/0xE9) 2) M0.C0 Temp Sensor TPM432 (0x98/0x99) 3) M0.C1 Temp Sensor TPM432 (0x98/0x99) 4) M0.C2 Temp Sensor TPM432 (0x98/0x99)
0x324	1	I2C_PRSCL_HI_REG	I2C-Ch1
0x328	1	I2C_CTRL_REG	I2C-Ch1
0x32C	0	I2C_TX_REG	I2C-Ch1
0x32C	1	I2C_RX_REG	I2C-Ch1
0x330	0	I2C_CMD_REG	I2C-Ch1
0x330	1	I2C_STAT_REG	I2C-Ch1
0x334	1	I2C_MUX_SEL_REG	I2C-Ch1
0x338	1	I2C_RST_REG	I2C-Ch1
0x33C	1	SEM_REG	I2C-Ch1
0x340	1	I2C_PRSCL_LO_REG	I2C-Ch2	SWB_0 1) SWB_FPGA - FPGA (0x80/0x81) 2) IO Exp - PCA9555 (0x48/0x49)
0x344	1	I2C_PRSCL_HI_REG	I2C-Ch2
0x348	1	I2C_CTRL_REG	I2C-Ch2
0x34C	0	I2C_TX_REG	I2C-Ch2
0x34C	1	I2C_RX_REG	I2C-Ch2
0x350	0	I2C_CMD_REG	I2C-Ch2
0x350	1	I2C_STAT_REG	I2C-Ch2
0x354	1	I2C_MUX_SEL_REG	I2C-Ch2
0x358	1	I2C_RST_REG	I2C-Ch2
0x35C	1	SEM_REG	I2C-Ch2
0x360	1	I2C_PRSCL_LO_REG	I2C-Ch3	SWB_1 1) SWB_FPGA - FPGA (0x80/0x81) 2) IO Exp - PCA9555 (0x48/0x49)
0x364	1	I2C_PRSCL_HI_REG	I2C-Ch3
0x368	1	I2C_CTRL_REG	I2C-Ch3
0x36C	0	I2C_TX_REG	I2C-Ch3
0x36C	1	I2C_RX_REG	I2C-Ch3
0x370	0	I2C_CMD_REG	I2C-Ch3
0x370	1	I2C_STAT_REG	I2C-Ch3
0x374	1	I2C_MUX_SEL_REG	I2C-Ch3
0x378	1	I2C_RST_REG	I2C-Ch3
0x37C	1	SEM_REG	I2C-Ch3
0x380	1	I2C_PRSCL_LO_REG	I2C-Ch4	SWB_0 1) M1 4ch I2C MUX TCA9546 (0xE8/0xE9) 2) M1.C0 Clk GEN - SI5363A (0xB0/0xB1) Clk GEN - SI5363A (0xB2/0xB3) Tray Catridge - EEPROM (0xA0/0xA1) 3) M1.C1 Clk GEN - SI5363A (0xB4/0xB5) Clk GEN - SI5363A (0xB6/0xB7) Clk GEN - SI5363A (0xB8/0xB9) Tray Catridge - EEPROM (0xA0/0xA1) 4) M1.C2 SWB EEPROM (0xA0/0xA1)
0x384	1	I2C_PRSCL_HI_REG	I2C-Ch4
0x388	1	I2C_CTRL_REG	I2C-Ch4
0x38C	0	I2C_TX_REG	I2C-Ch4
0x38C	1	I2C_RX_REG	I2C-Ch4
0x390	0	I2C_CMD_REG	I2C-Ch4
0x390	1	I2C_STAT_REG	I2C-Ch4
0x394	1	I2C_MUX_SEL_REG	I2C-Ch4
0x398	1	I2C_RST_REG	I2C-Ch4
0x39C	1	SEM_REG	I2C-Ch4
0x3A0	1	I2C_PRSCL_LO_REG	I2C-Ch5	SWB_1 1) M1 4ch I2C MUX TCA9546 (0xE8/0xE9) 2) M1.C0 Clk GEN - SI5363A (0xB0/0xB1) Clk GEN - SI5363A (0xB2/0xB3) Tray Catridge - EEPROM (0xA0/0xA1) 3) M1.C1 Clk GEN - SI5363A (0xB4/0xB5) Clk GEN - SI5363A (0xB6/0xB7) Clk GEN - SI5363A (0xB8/0xB9) Tray Catridge - EEPROM (0xA0/0xA1) 4) M1.C2 SWB EEPROM (0xA0/0xA1)
0x3A4	1	I2C_PRSCL_HI_REG	I2C-Ch5
0x3A8	1	I2C_CTRL_REG	I2C-Ch5
0x3AC	0	I2C_TX_REG	I2C-Ch5
0x3AC	1	I2C_RX_REG	I2C-Ch5
0x3B0	0	I2C_CMD_REG	I2C-Ch5
0x3B0	1	I2C_STAT_REG	I2C-Ch5
0x3B4	1	I2C_MUX_SEL_REG	I2C-Ch5
0x3B8	1	I2C_RST_REG	I2C-Ch5
0x3BC	1	SEM_REG	I2C-Ch5
0x3C0	1	I2C_PRSCL_LO_REG	I2C-Ch6	SWB_0 1) VRM - M29816 (0x40/0x41) 2) VRM - M2985B (0x42/0x43) 3) VRM - M2985B (0x44/0x45) 4) VRM - M2985B (0x46/0x47) 5) VRM - M2985B (0x48/0x49)
0x3C4	1	I2C_PRSCL_HI_REG	I2C-Ch6
0x3C8	1	I2C_CTRL_REG	I2C-Ch6
0x3CC	0	I2C_TX_REG	I2C-Ch6
0x3CC	1	I2C_RX_REG	I2C-Ch6
0x3D0	0	I2C_CMD_REG	I2C-Ch6
0x3D0	1	I2C_STAT_REG	I2C-Ch6
0x3D4	1	I2C_MUX_SEL_REG	I2C-Ch6
0x3D8	1	I2C_RST_REG	I2C-Ch6
0x3DC	1	SEM_REG	I2C-Ch6
0x3E0	1	I2C_PRSCL_LO_REG	I2C-Ch7	SWB_1 1) VRM - M29816 (0x40/0x41) 2) VRM - M2985B (0x42/0x43) 3) VRM - M2985B (0x44/0x45) 4) VRM - M2985B (0x46/0x47) 5) VRM - M2985B (0x48/0x49)
0x3E4	1	I2C_PRSCL_HI_REG	I2C-Ch7
0x3E8	1	I2C_CTRL_REG	I2C-Ch7
0x3EC	0	I2C_TX_REG	I2C-Ch7
0x3EC	1	I2C_RX_REG	I2C-Ch7
0x3F0	0	I2C_CMD_REG	I2C-Ch7
0x3F0	1	I2C_STAT_REG	I2C-Ch7
0x3F4	1	I2C_MUX_SEL_REG	I2C-Ch7
0x3F8	1	I2C_RST_REG	I2C-Ch7
0x3FC	1	SEM_REG	I2C-Ch7
0x400	1	I2C_PRSCL_LO_REG	I2C-Ch8	SWB_0 1) VRM - M2985B (0x4A/0x4B) 2) VRM - M2985B (0x4C/0x4D) 3) VRM - M2985B (0x4E/0x4F) 4) VRM - M2985B (0x50/0x51) 5) VRM - M2985B (0x52/0x53)
0x404	1	I2C_PRSCL_HI_REG	I2C-Ch8
0x408	1	I2C_CTRL_REG	I2C-Ch8
0x40C	0	I2C_TX_REG	I2C-Ch8
0x40C	1	I2C_RX_REG	I2C-Ch8
0x410	0	I2C_CMD_REG	I2C-Ch8
0x410	1	I2C_STAT_REG	I2C-Ch8
0x414	1	I2C_MUX_SEL_REG	I2C-Ch8
0x418	1	I2C_RST_REG	I2C-Ch8
0x41C	1	SEM_REG	I2C-Ch8
0x420	1	I2C_PRSCL_LO_REG	I2C-Ch9	SWB_1 1) VRM - M2985B (0x4A/0x4B) 2) VRM - M2985B (0x4C/0x4D) 3) VRM - M2985B (0x4E/0x4F) 4) VRM - M2985B (0x50/0x51) 5) VRM - M2985B (0x52/0x53)
0x424	1	I2C_PRSCL_HI_REG	I2C-Ch9
0x428	1	I2C_CTRL_REG	I2C-Ch9
0x42C	0	I2C_TX_REG	I2C-Ch9
0x42C	1	I2C_RX_REG	I2C-Ch9
0x430	0	I2C_CMD_REG	I2C-Ch9
0x430	1	I2C_STAT_REG	I2C-Ch9
0x434	1	I2C_MUX_SEL_REG	I2C-Ch9
0x438	1	I2C_RST_REG	I2C-Ch9
0x43C	1	SEM_REG	I2C-Ch9
0x440	1	I2C_PRSCL_LO_REG	I2C-Ch10	1) M0 2ch I2C MUX - TCA9543 (0xE1/0xE0) 2) M0.C0 Clk Buf - 9DBL0452 (0xD6/0xD7) M0.C0 Clk Buf - 9DBL0452 (0xDA/0xDB) 3) M1.C1 Fan Ctrl - MAX31790 (0x40/0x41) Temp Sensor - TMP75 (0x90/0x91) Temp Sensor - TMP75 (0x92/0x93) Temp Sensor - TM432 (0x98/0x99)
0x444	1	I2C_PRSCL_HI_REG	I2C-Ch10
0x448	1	I2C_CTRL_REG	I2C-Ch10
0x44C	0	I2C_TX_REG	I2C-Ch10
0x44C	1	I2C_RX_REG	I2C-Ch10
0x450	0	I2C_CMD_REG	I2C-Ch10
0x450	1	I2C_STAT_REG	I2C-Ch10
0x454	1	I2C_MUX_SEL_REG	I2C-Ch10
0x458	1	I2C_RST_REG	I2C-Ch10
0x45C	1	SEM_REG	I2C-Ch10
0x460	1	I2C_PRSCL_LO_REG	I2C-Ch11	1) Fan Ctrl - MAX31790 (0x40/0x41)
0x464	1	I2C_PRSCL_HI_REG	I2C-Ch11
0x468	1	I2C_CTRL_REG	I2C-Ch11
0x46C	0	I2C_TX_REG	I2C-Ch11
0x46C	1	I2C_RX_REG	I2C-Ch11
0x470	0	I2C_CMD_REG	I2C-Ch11
0x470	1	I2C_STAT_REG	I2C-Ch11
0x474	1	I2C_MUX_SEL_REG	I2C-Ch11
0x478	1	I2C_RST_REG	I2C-Ch11
0x47C	1	SEM_REG	I2C-Ch11
0x480	1	I2C_PRSCL_LO_REG	I2C-Ch12	1) ADC leakage - ADC128D818 (0x3E/0x3F)
0x484	1	I2C_PRSCL_HI_REG	I2C-Ch12
0x488	1	I2C_CTRL_REG	I2C-Ch12
0x48C	0	I2C_TX_REG	I2C-Ch12
0x48C	1	I2C_RX_REG	I2C-Ch12
0x490	0	I2C_CMD_REG	I2C-Ch12
0x490	1	I2C_STAT_REG	I2C-Ch12
0x494	1	I2C_MUX_SEL_REG	I2C-Ch12
0x498	1	I2C_RST_REG	I2C-Ch12
0x49C	1	SEM_REG	I2C-Ch12
0x4A0	1	I2C_PRSCL_LO_REG	I2C-Ch13	1) NFC SM-MFAD4-C02 (0x50/0x51)
0x4A4	1	I2C_PRSCL_HI_REG	I2C-Ch13
0x4A8	1	I2C_CTRL_REG	I2C-Ch13
0x4AC	0	I2C_TX_REG	I2C-Ch13
0x4AC	1	I2C_RX_REG	I2C-Ch13
0x4B0	0	I2C_CMD_REG	I2C-Ch13
0x4B0	1	I2C_STAT_REG	I2C-Ch13
0x4B4	1	I2C_MUX_SEL_REG	I2C-Ch13
0x4B8	1	I2C_RST_REG	I2C-Ch13
0x4BC	1	SEM_REG	I2C-Ch13
0x4C0	1	I2C_PRSCL_LO_REG	I2C-Ch14	1) M1 2ch I2C MUX - TCA9543 (0xE1/0xE0) 2) M1.C0 QSFP28.P1 Xcvr (0xA1/0xA0) 3) M1.C1 QSFP28.P2 Xcvr (0xA1/0xA0)
0x4C4	1	I2C_PRSCL_HI_REG	I2C-Ch14
0x4C8	1	I2C_CTRL_REG	I2C-Ch14
0x4CC	0	I2C_TX_REG	I2C-Ch14
0x4CC	1	I2C_RX_REG	I2C-Ch14
0x4D0	0	I2C_CMD_REG	I2C-Ch14
0x4D0	1	I2C_STAT_REG	I2C-Ch14
0x4D4	1	I2C_MUX_SEL_REG	I2C-Ch14
0x4D8	1	I2C_RST_REG	I2C-Ch14
0x4DC	1	SEM_REG	I2C-Ch14
0x4E0	1	I2C_PRSCL_LO_REG	I2C-Ch15	1) Fan1 EFUSE - STEF48H28 (0x20/0x21) 2) Fan2 EFUSE - STEF48H28 (0x22/0x23) 3) Fan3 EFUSE - STEF48H28 (0x80/0x81)
0x4E4	1	I2C_PRSCL_HI_REG	I2C-Ch15
0x4E8	1	I2C_CTRL_REG	I2C-Ch15
0x4EC	0	I2C_TX_REG	I2C-Ch15
0x4EC	1	I2C_RX_REG	I2C-Ch15
0x4F0	0	I2C_CMD_REG	I2C-Ch15
0x4F0	1	I2C_STAT_REG	I2C-Ch15
0x4F4	1	I2C_MUX_SEL_REG	I2C-Ch15
0x4F8	1	I2C_RST_REG	I2C-Ch15
0x4FC	1	SEM_REG	I2C-Ch15
0x500	1	I2C_PRSCL_LO_REG	I2C-Ch16	1) 1G PHY - I210 Ethernet Controller (0x92/0x93)
0x504	1	I2C_PRSCL_HI_REG	I2C-Ch16
0x508	1	I2C_CTRL_REG	I2C-Ch16
0x50C	0	I2C_TX_REG	I2C-Ch16
0x50C	1	I2C_RX_REG	I2C-Ch16
0x510	0	I2C_CMD_REG	I2C-Ch16
0x510	1	I2C_STAT_REG	I2C-Ch16
0x514	1	I2C_MUX_SEL_REG	I2C-Ch16
0x518	1	I2C_RST_REG	I2C-Ch16
0x51C	1	SEM_REG	I2C-Ch16
0x520	1	I2C_PRSCL_LO_REG	I2C-Ch17	1) Chassis EEPROM (0x50/0x51/0x52/0x53) 2) Diag EEPROM (0x57) 3) MGIN CHIP1- (0xB8/0xB9) MGIN CHIP2- (0xBC/0xBD) MGIN CHIP3- (0xC4/0xC5) MGIN CHIP4- (0xC8/0xC9)
0x524	1	I2C_PRSCL_HI_REG	I2C-Ch17
0x528	1	I2C_CTRL_REG	I2C-Ch17
0x52C	0	I2C_TX_REG	I2C-Ch17
0x52C	1	I2C_RX_REG	I2C-Ch17
0x530	0	I2C_CMD_REG	I2C-Ch17
0x530	1	I2C_STAT_REG	I2C-Ch17
0x534	1	I2C_MUX_SEL_REG	I2C-Ch17
0x538	1	I2C_RST_REG	I2C-Ch17
0x53C	1	SEM_REG	I2C-Ch17
0x540	144	RSVD	RSVD
0x780	1	I2C_PRSCL_LO_REG	VI2C-ICB-Ch0	Mapped to ICBX_X VI2C_DEV_ID 8'h21
0x784	1	I2C_PRSCL_HI_REG	VI2C-ICB-Ch0	1) PDB Fan Controller
0x788	1	I2C_CTRL_REG	VI2C-ICB-Ch0
0x78C	0	I2C_TX_REG	VI2C-ICB-Ch0
0x78C	1	I2C_RX_REG	VI2C-ICB-Ch0
0x790	0	I2C_CMD_REG	VI2C-ICB-Ch0
0x790	1	I2C_STAT_REG	VI2C-ICB-Ch0
0x794	1	I2C_MUX_SEL_REG	VI2C-ICB-Ch0
0x798	1	I2C_RST_REG	VI2C-ICB-Ch0
0x79C	1	RSVD	VI2C-ICB-Ch0
0x7A0	1	I2C_PRSCL_LO_REG	VI2C-ICB-Ch1	Mapped to ICBX_X VI2C_DEV_ID 8'h23
0x7A4	1	I2C_PRSCL_HI_REG	VI2C-ICB-Ch1	1) PDB EEPROM
0x7A8	1	I2C_CTRL_REG	VI2C-ICB-Ch1
0x7AC	0	I2C_TX_REG	VI2C-ICB-Ch1
0x7AC	1	I2C_RX_REG	VI2C-ICB-Ch1
0x7B0	0	I2C_CMD_REG	VI2C-ICB-Ch1
0x7B0	1	I2C_STAT_REG	VI2C-ICB-Ch1
0x7B4	1	I2C_MUX_SEL_REG	VI2C-ICB-Ch1
0x7B8	1	I2C_RST_REG	VI2C-ICB-Ch1
0x7BC	1	RSVD	VI2C-ICB-Ch1
0x7C0	1	I2C_PRSCL_LO_REG	VI2C-ICB-Ch2	Mapped to ICBX_X VI2C_DEV_ID 8'h25
0x7C4	1	I2C_PRSCL_HI_REG	VI2C-ICB-Ch2	1) PDB external temperature sensors
0x7C8	1	I2C_CTRL_REG	VI2C-ICB-Ch2
0x7CC	0	I2C_TX_REG	VI2C-ICB-Ch2
0x7CC	1	I2C_RX_REG	VI2C-ICB-Ch2
0x7D0	0	I2C_CMD_REG	VI2C-ICB-Ch2
0x7D0	1	I2C_STAT_REG	VI2C-ICB-Ch2
0x7D4	1	I2C_MUX_SEL_REG	VI2C-ICB-Ch2
0x7D8	1	I2C_RST_REG	VI2C-ICB-Ch2
0x7DC	1	RSVD	VI2C-ICB-Ch2
0x7E0	1	I2C_PRSCL_LO_REG	VI2C-ICB-Ch3	Mapped to ICBX_X VI2C_DEV_ID 8'h27
0x7E4	1	I2C_PRSCL_HI_REG	VI2C-ICB-Ch3	1) Hotswap controller
0x7E8	1	I2C_CTRL_REG	VI2C-ICB-Ch3
0x7EC	0	I2C_TX_REG	VI2C-ICB-Ch3
0x7EC	1	I2C_RX_REG	VI2C-ICB-Ch3
0x7F0	0	I2C_CMD_REG	VI2C-ICB-Ch3
0x7F0	1	I2C_STAT_REG	VI2C-ICB-Ch3
0x7F4	1	I2C_MUX_SEL_REG	VI2C-ICB-Ch3
0x7F8	1	I2C_RST_REG	VI2C-ICB-Ch3
0x7FC	1	RSVD	VI2C-ICB-Ch3
0x800	1	I2C_PRSCL_LO_REG	VI2C-ICB-Ch4	Mapped to ICBX_X VI2C_DEV_ID 8'h29
0x804	1	I2C_PRSCL_HI_REG	VI2C-ICB-Ch4	1) Power bricks and EFUSE
0x808	1	I2C_CTRL_REG	VI2C-ICB-Ch4
0x80C	0	I2C_TX_REG	VI2C-ICB-Ch4
0x80C	1	I2C_RX_REG	VI2C-ICB-Ch4
0x810	0	I2C_CMD_REG	VI2C-ICB-Ch4
0x810	1	I2C_STAT_REG	VI2C-ICB-Ch4
0x814	1	I2C_MUX_SEL_REG	VI2C-ICB-Ch4
0x818	1	I2C_RST_REG	VI2C-ICB-Ch4
0x81C	1	RSVD	VI2C-ICB-Ch4
0x820	1	RSVD	RSVD

SWB — Switch Board

SWB — Function none

Offset	DW	Register	Group	Comment
0x000	1	FPGA_REV_ID_REG	GEN & ID
0x004	1	RSVD	GEN & ID
0x008	1	RSVD	GEN & ID
0x00C	1	SWB_INFO_REG	GEN & ID
0x010	1	RSVD	GEN & ID
0x014	11	RSVD	GEN & ID
0x040	16	RSVD	GEN & ID
0x080	1	FPGA_RECONFIG_CTRL_REG	FPGA Reconfig
0x084	1	FPGA_RECONFIG_STAT_REG	FPGA Reconfig
0x088	6	RSVD	FPGA Reconfig
0x0A0	1	RSVD	FPGA Reconfig
0x0A4	1	RSVD	FPGA Reconfig
0x0A8	6	RSVD	FPGA Reconfig
0x0C0	1	SCRTCH_0_REG	Scratchpad
0x0C4	1	SCRTCH_1_REG	Scratchpad
0x0C8	1	SCRTCH_2_REG	Scratchpad
0x0CC	1	SCRTCH_3_REG	Scratchpad
0x0D0	12	RSVD	Scratchpad
0x100	96	RSVD	MSI INT
0x280	32	RSVD	Mailbox
0x300	1	RSVD	Power
0x304	1	PWR_STAT_REG	Power
0x308	1	PWR_STAT_PLRTY_REG	Power
0x30C	1	PWR_STAT_EDG_LVL_REG	Power
0x310	1	PWR_STAT_INT_EN_REG	Power
0x314	1	PWR_STAT_INT_STAT_REG	Power
0x318	1	PWR_STAT_INT_CLR_REG	Power
0x31C	1	SEM_REG	Power
0x320	8	RSVD	Power
0x340	1	RSVD	Speed Sense
0x344	1	RSVD	Speed Sense
0x348	14	RSVD	Speed Sense
0x380	1	CB_CTRL_REG	CB
0x384	1	CB_STAT_REG	CB	384
0x388	1	CB_STAT_PLRTY_REG	CB
0x38C	1	CB_STAT_EDG_LVL_REG	CB
0x390	1	CB_STAT_INT_EN_REG	CB
0x394	1	CB_STAT_INT_STAT_REG	CB
0x398	1	CB_STAT_INT_CLR_REG	CB
0x39C	1	SEM_REG	CB
0x3A0	8	RSVD	CB
0x3C0	1	ASIC_CTRL_REG	ASIC
0x3C4	1	ASIC_STAT_REG	ASIC
0x3C8	1	ASIC_STAT_PLRTY_REG	ASIC
0x3CC	1	ASIC_STAT_EDG_LVL_REG	ASIC
0x3D0	1	ASIC_STAT_INT_EN_REG	ASIC
0x3D4	1	ASIC_STAT_INT_STAT_REG	ASIC
0x3D8	1	ASIC_STAT_INT_CLR_REG	ASIC
0x3DC	1	SEM_REG	ASIC
0x3E0	8	RSVD	ASIC
0x400	1	RTM_CTRL_REG	Retimer
0x404	1	RSVD	Retimer
0x408	1	RSVD	Retimer
0x40C	1	RSVD	Retimer
0x410	1	RSVD	Retimer
0x414	1	RSVD	Retimer
0x418	1	RSVD	Retimer
0x41C	1	RSVD	Retimer
0x420	8	RSVD	Retimer
0x440	1	RSVD	Thermal
0x444	1	THRM_STAT_REG	Thermal
0x448	1	THRM_STAT_PLRTY_REG	Thermal
0x44C	1	THRM_STAT_EDG_LVL_REG	Thermal
0x450	1	THRM_STAT_INT_EN_REG	Thermal
0x454	1	THRM_STAT_INT_STAT_REG	Thermal
0x458	1	THRM_STAT_INT_CLR_REG	Thermal
0x45C	1	SEM_REG	Thermal
0x460	8	RSVD	Thermal
0x480	128	RSVD	RSVD
0x680	1	RSVD	Other Dev ctrl-stat-int	680
0x684	1	RSVD	Other Dev ctrl-stat-int
0x688	1	RSVD	Other Dev ctrl-stat-int
0x68C	1	EN_ACCSS_PRTCTD_REG	Other Dev ctrl-stat-int
0x690	12	I2C_MUX_RST_REG	Other Dev ctrl-stat-int
0x6C0	1	SPI_MUX_REG	Other Dev ctrl-stat-int
0x6C4	1	RSVD	Other Dev ctrl-stat-int
0x6C8	270	RSVD	RSVD
0xB00	1	FLSH_CTRL_REG	Flash Write Protect
0xB04	31	RSVD	Flash Write Protect
0xB80	32	RSVD	LED
0xC00	1	RSVD	Debug & Test
0xC04	1	RSVD	Debug & Test
0xC08	1	TND_PWR_CTRL_0_REG	Debug & Test
0xC0C	1	TND_PWR_CTRL_1_REG	Debug & Test
0xC10	1	TND_PWR_STAT_0_REG	Debug & Test
0xC14	1	TND_PWR_STAT_1_REG	Debug & Test
0xC18	1	TND_PWR_STAT_2_REG	Debug & Test
0xC1C	1	TND_PWR_STAT_3_REG	Debug & Test
0xC20	1	TND_CB_GPIO_CTRL_REG	Debug & Test
0xC24	1	TND_CB_GPIO_STAT_REG	Debug & Test
0xC28	1	TND_CB_GPIO_DIR_CTRL_REG	Debug & Test
0xC2C	89	RSVD	Debug & Test
0xD90	1	RST_CAUSE_REG	Reset Stat
0xD94	31	RSVD	Reset Stat
0xE10	56	RSVD	RSVD

ICB — PDB / Power Distribution Board

ICB — Function none

Offset	DW	Register	Group	Comment
0x000	1	FPGA_REV_ID_REG	GEN & ID	ICB_BP FPGA revision & Id register
0x004	1	RSVD	GEN & ID
0x008	1	RSVD	GEN & ID
0x00C	1	RSVD	GEN & ID
0x010	28	RSVD	GEN & ID
0x080	1	FPGA_RECONFIG_CTRL_REG	FPGA Reconfig
0x084	1	FPGA_RECONFIG_STAT_REG	FPGA Reconfig
0x088	14	RSVD	FPGA Reconfig
0x0C0	1	SCRTCH_0_REG	Scratchpad
0x0C4	1	SCRTCH_1_REG	Scratchpad
0x0C8	1	SCRTCH_2_REG	Scratchpad
0x0CC	1	SCRTCH_3_REG	Scratchpad
0x0D0	12	RSVD	Scratchpad
0x100	96	RSVD	MSI INT
0x280	32	RSVD	Mailbox
0x300	1	PWR_CTRL_REG	Power ctrl-stat-int
0x304	1	PWR_STAT_REG	Power ctrl-stat-int
0x308	1	PWR_STAT_PLRTY_REG	Power ctrl-stat-int
0x30C	1	PWR_STAT_EDG_LVL_REG	Power ctrl-stat-int
0x310	1	PWR_STAT_INT_EN_REG	Power ctrl-stat-int
0x314	1	PWR_STAT_INT_STAT_REG	Power ctrl-stat-int
0x318	1	PWR_STAT_INT_CLR_REG	Power ctrl-stat-int
0x31C	1	SEM_REG	Power ctrl-stat-int
0x320	8	RSVD	Power ctrl-stat-int
0x340	1	FAN_CTRL_REG	Fan ctrl-stat-int
0x344	1	FAN_STAT_REG	Fan ctrl-stat-int
0x348	1	FAN_STAT_PLRTY_REG	Fan ctrl-stat-int
0x34C	1	FAN_STAT_EDG_LVL_REG	Fan ctrl-stat-int
0x350	1	FAN_STAT_INT_EN_REG	Fan ctrl-stat-int
0x354	1	FAN_STAT_INT_STAT_REG	Fan ctrl-stat-int
0x358	1	FAN_STAT_INT_CLR_REG	Fan ctrl-stat-int
0x35C	1	SEM_REG	Fan ctrl-stat-int
0x360	1	RSVD	Thermal
0x364	1	THRM_STAT_REG	Thermal
0x368	1	THRM_STAT_PLRTY_REG	Thermal
0x36C	1	THRM_STAT_EDG_LVL_REG	Thermal
0x370	1	THRM_STAT_INT_EN_REG	Thermal
0x374	1	THRM_STAT_INT_STAT_REG	Thermal
0x378	1	THRM_STAT_INT_CLR_REG	Thermal
0x37C	1	SEM_REG	Thermal
0x380	8	RSVD	Thermal
0x3A0	184	RSVD	RSVD
0x680	1	RSVD	Other Dev ctrl-stat-int
0x684	1	RSVD	Other Dev ctrl-stat-int
0x688	1	RSVD	Other Dev ctrl-stat-int
0x68C	1	EN_ACCSS_PRTCTD_REG	Other Dev ctrl-stat-int
0x690	1	I2C_MUX_RST_REG	Other Dev ctrl-stat-int
0x694	12	RSVD	Other Dev ctrl-stat-int
0x6C4	1	RSVD	Other Dev ctrl-stat-int
0x6C8	270	RSVD	RSVD
0xB00	1	FLSH_CTRL_REG	Flash Write Protect
0xB04	31	RSVD	Flash Write Protect
0xB80	1	LED_SYNC_REG	LED
0xB84	1	LED_CONFIG_REG	LED	B84
0xB88	1	LED_CTRL_0_REG	LED	B88
0xB8C	1	RSVD	LED	B8C
0xB90	1	RSVD	LED	B90
0xB94	27	RSVD	LED
0xC00	1	RSVD	Debug & Test
0xC04	1	RSVD	Debug & Test
0xC08	1	RSVD	Debug & Test
0xC0C	1	RSVD	Debug & Test
0xC10	1	RSVD	Debug & Test
0xC14	1	RSVD	Debug & Test
0xC18	1	RSVD	Debug & Test
0xC1C	1	RSVD	Debug & Test
0xC20	1	TND_CB_GPIO_CTRL_REG	Debug & Test
0xC24	1	TND_CB_GPIO_STAT_REG	Debug & Test
0xC28	1	TND_CB_GPIO_DIR_CTRL_REG	Debug & Test
0xC2C	89	RSVD	Debug & Test
0xD90	1	RSVD	Reset Stat
0xD94	1	RSVD	Reset Stat
0xD98	26	RSVD	RSVD
0xE00	1	I2C_PRSCL_LO_REG	I2C-Ch0	1) PDB Fan Controller
0xE04	1	I2C_PRSCL_HI_REG	I2C-Ch0
0xE08	1	I2C_CTRL_REG	I2C-Ch0
0xE0C	0	I2C_TX_REG	I2C-Ch0
0xE0C	1	I2C_RX_REG	I2C-Ch0
0xE10	0	I2C_CMD_REG	I2C-Ch0
0xE10	1	I2C_STAT_REG	I2C-Ch0
0xE14	1	I2C_MUX_SEL_REG	I2C-Ch0
0xE18	1	I2C_RST_REG	I2C-Ch0
0xE1C	1	SEM_REG	I2C-Ch0
0xE20	1	I2C_PRSCL_LO_REG	I2C-Ch1	1) PDB EEPROM
0xE24	1	I2C_PRSCL_HI_REG	I2C-Ch1
0xE28	1	I2C_CTRL_REG	I2C-Ch1
0xE2C	0	I2C_TX_REG	I2C-Ch1
0xE2C	1	I2C_RX_REG	I2C-Ch1
0xE30	0	I2C_CMD_REG	I2C-Ch1
0xE30	1	I2C_STAT_REG	I2C-Ch1
0xE34	1	I2C_MUX_SEL_REG	I2C-Ch1
0xE38	1	I2C_RST_REG	I2C-Ch1
0xE3C	1	SEM_REG	I2C-Ch1
0xE40	1	I2C_PRSCL_LO_REG	I2C-Ch2	1) PDB external temperature sensors
0xE44	1	I2C_PRSCL_HI_REG	I2C-Ch2
0xE48	1	I2C_CTRL_REG	I2C-Ch2
0xE4C	0	I2C_TX_REG	I2C-Ch2
0xE4C	1	I2C_RX_REG	I2C-Ch2
0xE50	0	I2C_CMD_REG	I2C-Ch2
0xE50	1	I2C_STAT_REG	I2C-Ch2
0xE54	1	I2C_MUX_SEL_REG	I2C-Ch2
0xE58	1	I2C_RST_REG	I2C-Ch2
0xE5C	1	SEM_REG	I2C-Ch2
0xE60	1	I2C_PRSCL_LO_REG	I2C-Ch3	1) Hotswap controller
0xE64	1	I2C_PRSCL_HI_REG	I2C-Ch3
0xE68	1	I2C_CTRL_REG	I2C-Ch3
0xE6C	0	I2C_TX_REG	I2C-Ch3
0xE6C	1	I2C_RX_REG	I2C-Ch3
0xE70	0	I2C_CMD_REG	I2C-Ch3
0xE70	1	I2C_STAT_REG	I2C-Ch3
0xE74	1	I2C_MUX_SEL_REG	I2C-Ch3
0xE78	1	I2C_RST_REG	I2C-Ch3
0xE7C	1	SEM_REG	I2C-Ch3
0xE80	1	I2C_PRSCL_LO_REG	I2C-Ch4	1) Power bricks and EFUSE
0xE84	1	I2C_PRSCL_HI_REG	I2C-Ch4
0xE88	1	I2C_CTRL_REG	I2C-Ch4
0xE8C	0	I2C_TX_REG	I2C-Ch4
0xE8C	1	I2C_RX_REG	I2C-Ch4
0xE90	0	I2C_CMD_REG	I2C-Ch4
0xE90	1	I2C_STAT_REG	I2C-Ch4
0xE94	1	I2C_MUX_SEL_REG	I2C-Ch4
0xE98	1	I2C_RST_REG	I2C-Ch4
0xE9C	1	SEM_REG	I2C-Ch4

Common

none — Function none

Offset	DW	Register	Group	Comment
0x		none	none	Start of next device
0x	none	none	none	Start of next device
0x		none	none	Start of next device

4. MSI Interrupt Mapping

CB MSI Vector Map

Interface	CB Register	Function	MSI Vector (Function.Vector.Bit)	Signal Description
Power	PWR_STAT_REG	0	0.0.0	Power Stat Interrupt
TPM	TPM_STAT_REG	0	0.1.0	TPM Stat Interrupt
PMC	PMC_STAT_REG	0	0.2.0	PMCC Stat Interrupt
ICB	ICB_STAT_REG	0	0.3.0	ICB Stat Interrupt
SWB 0	SWB_STAT_REG	0	0.4.0	SWB 0 Stat Interrupt
SWB 1	SWB_STAT_REG	0	0.5.0	SWB 1 Stat Interrupt
Thermal	THRM_STAT_REG	0	0.6.0	Thermal Stat Interrupt
USB	USB_STAT_REG	0	0.7.0	USB Stat Interrupt
Button	BTC_STAT_REG	0	0.8.0	Button Stat Interrupt
Leak	LEAK_STAT_REG	0	0.9.0	Leak Stat Interrupt
NFC	NFC_STAT_REG	0	0.10.0	NFC Stat Interrupt
Intrusion	INTRD_STAT_REG	0	0.11.0	Intrusion Stat Interrupt
Battery	BTRY_STAT_REG	0	0.12.0	Battery Stat Interrupt
Fan	FAN_STAT_REG	1	1.0.0	Fan Stat Interrupt
Retimer	RTM_STAT_REG	1	1.1.0	Retimer Stat Interrupt
Ethernet Controller	ETH_CTRLR_STAT_REG	1	1.2.0	Ethernet Controller Stat Interrupt
1			1.3.0
1			1.4.0
1			1.5.0
		1	1.6.0
		1	1.7.0
User Port Power	USRPRT_PWR_STAT_REG	1	1.8.0	UserPort Power Stat Interrupt
User Port 0	USRPRT_0_STAT_REG	1	1.9.0	UserPort 0 Stat Interrupt
User Port 1	USRPRT_0_STAT_REG	1	1.10.0	UserPort 1 Stat Interrupt
1			1.11.0
SPI Flash Controller	SPI_CMD_STAT_REG	2	2.0.0	CB SPI Flash Controller Stat Interrupt
VSPI Flash Controller	SPI_CMD_STAT_REG	2	2.0.1	PMC VSPI Flash Controller Stat Interrupt
VSPI Flash Controller	SPI_CMD_STAT_REG	2	2.0.2	ICB VSPI Flash Controller Stat Interrupt
VSPI Flash Controller	SPI_CMD_STAT_REG	2	2.0.3	SWB0 VSPI Flash Controller Stat Interrupt
VSPI Flash Controller	SPI_CMD_STAT_REG	2	2.0.4	SWB1 VSPI Flash Controller Stat Interrupt
		2	2.0.5
		2	2.0.6
		2	2.0.7
		2	2.0.8
		2	2.0.9
		2	2.0.10
		2	2.0.11
		2	2.0.12
I2C	I2C_STAT_REG	3	3.0.0	Open core I2C Interrupt Ch0
I2C	I2C_STAT_REG	3	3.0.1	Open core I2C Interrupt Ch1
I2C	I2C_STAT_REG	3	3.0.2	Open core I2C Interrupt Ch2
I2C	I2C_STAT_REG	3	3.0.3	Open core I2C Interrupt Ch3
I2C	I2C_STAT_REG	3	3.0.4	Open core I2C Interrupt Ch4
I2C	I2C_STAT_REG	3	3.0.5	Open core I2C Interrupt Ch5
I2C	I2C_STAT_REG	3	3.0.6	Open core I2C Interrupt Ch6
I2C	I2C_STAT_REG	3	3.0.7	Open core I2C Interrupt Ch7
I2C	I2C_STAT_REG	3	3.0.8	Open core I2C Interrupt Ch8
I2C	I2C_STAT_REG	3	3.0.9	Open core I2C Interrupt Ch9
I2C	I2C_STAT_REG	3	3.0.10	Open core I2C Interrupt Ch10
I2C	I2C_STAT_REG	3	3.0.11	Open core I2C Interrupt Ch11
I2C	I2C_STAT_REG	3	3.0.12	Open core I2C Interrupt Ch12
I2C	I2C_STAT_REG	3	3.0.13	Open core I2C Interrupt Ch13
I2C	I2C_STAT_REG	3	3.0.14	Open core I2C Interrupt Ch14
I2C	I2C_STAT_REG	3	3.0.15	Open core I2C Interrupt Ch15
I2C	I2C_STAT_REG	3	3.0.16	Open core I2C Interrupt Ch16
I2C	I2C_STAT_REG	3	3.0.17	Open core I2C Interrupt Ch17
		3	3.0.18
		3	3.0.19
VI2C	I2C_STAT_REG	3	3.0.20	ICB LSB VI2C Interrupt Ch0
VI2C	I2C_STAT_REG	3	3.0.21	ICB LSB VI2C Interrupt Ch1
VI2C	I2C_STAT_REG	3	3.0.22	ICB LSB VI2C Interrupt Ch2
VI2C	I2C_STAT_REG	3	3.0.23	ICB LSB VI2C Interrupt Ch3
VI2C	I2C_STAT_REG	3	3.0.24	ICB LSB VI2C Interrupt Ch4
		3	3.0.25
		3	3.0.26
3			3.0.27

SWB Interrupt Map

Interface	CB Register	Interrupt Method	SWB Register	Signal Description	Notes
Power & Thermal	SWB_STAT_REG [2] #SWB_INT	Pin	PWR_STAT_REG THRM_STAT_REG

ICB Interrupt Map

Interface	CB Register	Interrupt Method	SWB Register	Signal Description	Notes
Power & Thermal	ICB_STAT_REG [2] #ICB_INT	Pin	PWR_STAT_REG FAN_STAT_REG THRM_STAT_REG

5. Register Descriptions

MSI Interrupts

Interrupt registers

MSI vector number assigned for each interrupt is predefined and not programmable.
There is a pair of DEV_MSI_PEND_REG and DEV_MSI_INT_EN_REG register for each MSI vector.
Each device within the function will have a PEND bit in one of the DEV_MSI_PEND_REG registers according to MSI vector number assigned to that device.
A device will have its PEND bit set when it is requesting service.
There can be as many as 32 pair of PEND/EN registers (one for each MSI interrupt vector) in a function. The actual number of MSI vectors reserved for each function is currently TBD.
PEND/EN registers are 32 bit registers but they can be extended to 64 bit if more than 32 interrupt request are assigned to a single MSI (A 64 bit register is composed of two 32-bit registers).

DEV_MSI_PEND_REG

There can be as many as 32 DEV_MSI_PEND_REG registers (one for each MSI interrupt vector) per function. Each device within the function will have a PEND bit in one of the PEND registers. A device will have its PEND bit set when it is requesting service.

Card Type: All · FPGA Type: All · Function: All · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
TBD		RO
TBD		RO

DEV_MSI_INT_EN_REG

There can be as many as 32 DEV_MSI_INT_EN_REG registers (one for each MSI interrupt vector) per function. The actual number of MSI vectors reserved for each function or device is currently TBD.

Enables a device to have its interrupt PEND status to trigger a MSI interrupt.

Card Type: All · FPGA Type: All · Function: All · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
TBD		RW
TBD		RW

MSI Generation

FPGA will trigger MSI interrupt only when (INT_EN [MSI_INDEX] & PEND [MSI_INDEX]) transition from 0 to 1. To avoid missing interrupts SW would make sure that it does not exit the ISR until the condition (INT_EN [MSI_INDEX] & PEND [MSI_INDEX]) is zero. Following examples clarifies how MSI interrupts are generated and serviced by FPGA and SW.

Scenario 1: Assume at time 0 no interrupt is pending and DEV1-INT is enabled (means its respective bit in DEV_MSI_INT_EN_REG is asserted). At time t1, PEND bit for DEV1-INT transitions from 0 to 1. Since enable bit is already 1, FPGA will detect 01 transition in (INT_EN & PEND) therefore will send MSI to CPU.

Scenario 2: Assume at time 0, DEV1-INT is pending but disabled. At time t1 SW set the DEV1-INT enable bit to 1. Since PEND bit is already 1, FPGA will detect 01 transition in (INT_EN & PEND) therefore will send MSI to CPU.

Scenario 3: Assume at time 0 no interrupt is pending and DEV1-INT and DEV2-INT are enabled (means their respective bits in DEV_MSI_INT_EN_REG are asserted). At time t1, PEND bit for DEV1-INT transitions from 0 to 1. Since enable bit is already 1, FPGA will detect 01 transition in (INT_EN & PEND) therefore will send MSI to CPU. Immediately after sending MSI and before SW can service DEV1-INT, at time t1+e, PEND bit for DEV2-INT transitions from 0 to 1. At time t1+e, (INT_EN & PEND) is already 1 and FPGA will not detect any 01 transition so no new MSI will be generated. At the time SW services the first MSI, it will check the PEND register and find out that DEV1-INT and DEV2-INT is pending and will service both interrupt requests before exiting the ISR.

Scenario 4: Assume at time 0 no interrupt is pending and DEV1-INT and DEV2-INT are enabled (means their respective bits in DEV_MSI_INT_EN_REG are asserted). At time t1, PEND bit for DEV1-INT transitions from 0 to 1. Since enable bit is already 1, FPGA will detect 01 transition in (INT_EN & PEND) therefore will send MSI to CPU. As part of ISR, SW will read PEND register and find out that Dev1-INT is pending. Before SW can fully service the DEV1-INT and clear the respective PEND bit, at time t2, PEND bit for DEV2-INT transitions from 0 to 1. At time t2, (INT_EN & PEND) is already 1 and FPGA will not detect any 01 transition so no new MSI will be generated. After SW cleared DEV1-INT before exiting the ISR, it will again read PEND register and find out that DEV2-INT is pending. SW will continue with servicing DEV2-INT before exiting the ISR.

Scenario 5: at Scenario 4, after SW cleared DEV1-INT (INT_EN & PEND transition from 1 to 0), immediately DEV2-INT happens. Before exiting ISR, SW will read the PEND register and detect the DEV2-INT but at the same time FPGA will detect 01 transition in (INT_EN & PEND) and send MSI. In this scenario SW services DEV2-INT as part of first MSI interrupt, therefore when SW process the second MSI it finds no pending INT because DEV2-INT has already been serviced by first MSI. This situation should be managed by SW.

LED Control bits

The status of each LED is defined by an 8-bit register as explained below:

Bit [0] – 0 off, 1 on

Bit [1] – 0 orange, 1 green or single color

Bit [2] – 0 not blink, 1 blink

Bit [3] – 0 slow blink, 1 fast blink

Bit [4] – 0 full bright, 1 half bright

Bit [5] – Reserved

Bit [7:6] – This bit is reserved unless stated in description

0 FPGA/SW Ctrl, other values (external control)

All LED register in this document use above codes to define the status of LED.

Common Register Description

FPGA_REV_ID_REG

Card Type: All · FPGA Type: All · Function: All · POR Value: See Description

Stores Device-ID & Revision Number for FPGA

Field	Bits	Type	Reset	Description
FPGA_ID	31:16	RO	See Description	Device Identification, CB = 0x2001 SWB = 0x2101 ICB = 0x2201
FPGA_REV	15:0	RO	0x0001	FPGA Code Revision field. Incremented by 1 in each revision. For lab Release, Rev will start with “1” illustrating beta version. e.g. 0x8001

RDND_MGMT_REG

Card Type: All · FPGA Type: All · Function: All · POR Value: 0xCCCC_CCCC

Redundancy Management Registers

Field	Bits	Type	Reset	Description
RDND_MGMT_STAT	31:0	RW	0xCCCC_CCCC	Under SW control

FUNC_CAP_0_REG

Card Type: All · FPGA Type: All · Function: All · POR Value: Defined per each function of each FPGA.

Defines the capability of PCIe function

Field	Bits	Type	Description
MSI_3_INT_NUM	31:24	RO	Illustrates the Number of interrupts that can generate MSI vector 3
MSI_2_INT_NUM	23:16	RO	Illustrates the Number of interrupts that can generate MSI vector 2
MSI_1_INT_NUM	15:8	RO	Illustrates the Number of interrupts that can generate MSI vector 1
MSI_0_INT_NUM	7:0	RO	Illustrates the Number of interrupts that can generate MSI vector 0

FUNC_CAP_1_REG

Card Type: All · FPGA Type: All · Function: All · POR Value: Defined per each function of each FPGA.

Defines the capability of PCIe function

Field	Bits	Type	Description
MSI_7_INT_NUM	31:24	RO	Illustrates the Number of interrupts that can generate MSI vector 7
MSI_6_INT_NUM	23:16	RO	Illustrates the Number of interrupts that can generate MSI vector 6
MSI_5_INT_NUM	15:8	RO	Illustrates the Number of interrupts that can generate MSI vector 5
MSI_4_INT_NUM	7:0	RO	Illustrates the Number of interrupts that can generate MSI vector 4

FUNC_CAP_2_REG

Card Type: All · FPGA Type: All · Function: All · POR Value: Defined per each function of each FPGA.

Defines the capability of PCIe function

Field	Bits	Type	Description
MSI_11_INT_NUM	31:24	RO	Illustrates the Number of interrupts that can generate MSI vector 11
MSI_10_INT_NUM	23:16	RO	Illustrates the Number of interrupts that can generate MSI vector 10
MSI_9_INT_NUM	15:8	RO	Illustrates the Number of interrupts that can generate MSI vector 9
MSI_8_INT_NUM	7:0	RO	Illustrates the Number of interrupts that can generate MSI vector 8

FUNC_CAP_3_REG

Card Type: All · FPGA Type: All · Function: All · POR Value: Defined per each function of each FPGA.

Defines the capability of PCIe function

Field	Bits	Type	Description
MSI_15_INT_NUM	31:24	RO	Illustrates the Number of interrupts that can generate MSI vector 15
MSI_14_INT_NUM	23:16	RO	Illustrates the Number of interrupts that can generate MSI vector 14
MSI_13_INT_NUM	15:8	RO	Illustrates the Number of interrupts that can generate MSI vector 13
MSI_12_INT_NUM	7:0	RO	Illustrates the Number of interrupts that can generate MSI vector 12

FUNC_CAP_4_REG

Card Type: All · FPGA Type: All · Function: All · POR Value: Defined per each function of each FPGA.

Defines the capability of PCIe function

Field	Bits	Type	Description
MSI_19_INT_NUM	31:24	RO	Illustrates the Number of interrupts that can generate MSI vector 19
MSI_18_INT_NUM	23:16	RO	Illustrates the Number of interrupts that can generate MSI vector 18
MSI_17_INT_NUM	15:8	RO	Illustrates the Number of interrupts that can generate MSI vector 17
MSI_16_INT_NUM	7:0	RO	Illustrates the Number of interrupts that can generate MSI vector 16

FUNC_CAP_5_REG

Card Type: All · FPGA Type: All · Function: All · POR Value: Defined per each function of each FPGA.

Defines the capability of PCIe function

Field	Bits	Type	Description
MSI_23_INT_NUM	31:24	RO	Illustrates the Number of interrupts that can generate MSI vector 23
MSI_22_INT_NUM	23:16	RO	Illustrates the Number of interrupts that can generate MSI vector 22
MSI_21_INT_NUM	15:8	RO	Illustrates the Number of interrupts that can generate MSI vector 21
MSI_20_INT_NUM	7:0	RO	Illustrates the Number of interrupts that can generate MSI vector 20

FUNC_CAP_6_REG

Card Type: All · FPGA Type: All · Function: All · POR Value: Defined per each function of each FPGA.

Defines the capability of PCIe function

Field	Bits	Type	Description
MSI_27_INT_NUM	31:24	RO	Illustrates the Number of interrupts that can generate MSI vector 27
MSI_26_INT_NUM	23:16	RO	Illustrates the Number of interrupts that can generate MSI vector 26
MSI_25_INT_NUM	15:8	RO	Illustrates the Number of interrupts that can generate MSI vector 25
MSI_24_INT_NUM	7:0	RO	Illustrates the Number of interrupts that can generate MSI vector 24

FUNC_CAP_7_REG

Card Type: All · FPGA Type: All · Function: All · POR Value: Defined per each function of each FPGA.

Defines the capability of PCIe function

Field	Bits	Type	Description
MSI_31_INT_NUM	31:24	RO	Illustrates the Number of interrupts that can generate MSI vector 31
MSI_30_INT_NUM	23:16	RO	Illustrates the Number of interrupts that can generate MSI vector 30
MSI_29_INT_NUM	15:8	RO	Illustrates the Number of interrupts that can generate MSI vector 29
MSI_28_INT_NUM	7:0	RO	Illustrates the Number of interrupts that can generate MSI vector 28

FUNC_CAP_8_REG

Card Type: All · FPGA Type: All · Function: All · POR Value: Defined for each function of each FPGA.

Defines the capability of PCIe function

Field	Bits	Type	Reset	Description
RSVD	31:8	RO		Reserved
NUM_OF_PRTS	7:0	RO		Represent the number of I2C ports in function 3. This is inclusive of real I2C ports, Virtual I2C Ports, and reserved I2C ports. This field is not used in other functions and will be always 0.

MBOX_n_DATA_REG

Data will be written in this register only if respective stat bit in MBOX_STAT_REG is showing empty stat. Write in this register will set the respective stat bit in MBOX_STAT_REG.

Card Type: All · FPGA Type: All · Function: 0 · POR Value: 0x0000_0000

Mailbox data

Field	Bits	Type	Reset	Description
DATA	31:0	RW	0

MBOX_STAT_REG

Card Type: All · FPGA Type: All · Function: 0 · POR Value: 0x0000_0000

Mailbox status

Field	Bits	Type	Description
RSVD	31:4	RO	Reserved
MBOX_3_STAT	3	W1C	1: MBOX_3_DATA_REG is full. 0: MBOX_3_DATA_REG is empty.
MBOX_2_STAT	2	W1C	Same as MBOX_3_STAT
MBOX_1_STAT	1	W1C	Same as MBOX_3_STAT
MBOX_0_STAT	0	W1C	Same as MBOX_3_STAT

MBOX_STAT_PLRTY_REG

Defines which level of the MBOX_STAT signal is the condition for triggering the Interrupt.

STAT_PLRTY_REG is defined once in this document. All other STAT_PLRTY_REG registers’ definition will be similar to this and their bits will follow their respective STAT_REG.

Card Type: All · FPGA Type: All · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Description
RSVD	31:4	RO	Reserved
MBOX_3_STAT_PLRTY	3	RW	1: means MBOX_3_STAT hi (1’b1) is the condition for triggering the interrupt. In case of edge interrupt a stat transition from lo to hi (1’b0 to 1’b1) is the condition for triggering the interrupt. 0: means MBOX_3_STAT lo (1’b0) is the condition for triggering the interrupt. In case of edge interrupt a stat transition from hi to lo (1’b1 to 1’b0) is the condition for triggering the interrupt.
MBOX_2_STAT_PLRTY	2	RW	Same as MBOX_3_STAT_PLRTY
MBOX_1_STAT_PLRTY	1	RW	Same as MBOX_3_STAT_PLRTY
MBOX_0_STAT_PLRTY	0	RW	Same as MBOX_3_STAT_PLRTY

MBOX_STAT_EDG_LVL_REG

Defines if the level or the transition of the MBOX_STAT signal is the condition for triggering the Interrupt.

STAT_EDG_LVL_REG is defined once in this document. All other STAT_EDG_LVL_REG registers’ definition will be similar to this and their bits will follow their respective STAT_REG.

Card Type: All · FPGA Type: All · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Description
RSVD	31:4	RO	Reserved
MBOX_3_STAT_EDG_LVL	3	RW	1: means the transition (or the edge) of MBOX_3_STAT is the condition for triggering the interrupt. 0: means the level of MBOX_3_STAT is the condition for triggering the interrupt.
MBOX_2_STAT_EDG_LVL	2	RW	Same as MBOX_3_STAT_EDG_LVL
MBOX_1_STAT_EDG_LVL	1	RW	Same as MBOX_3_STAT_EDG_LVL
MBOX_0_STAT_EDG_LVL	0	RW	Same as MBOX_3_STAT_EDG_LVL

MBOX_STAT_INT_EN_REG

Enable interrupts for status bits of mailboxes.

STAT_INT_EN_REG is defined once in this document. All other STAT_INT_EN_REG registers’ definition will be similar to this and their bits will follow their respective STAT_REG.

Card Type: All · FPGA Type: All · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Description
RSVD	31:4	RO	Reserved
MBOX_3_STAT_EN	3	RW	1: Enables MBOX_3_STAT to trigger interrupt if interrupt condition is met. 0: Disables MBOX_3_STAT interrupt.
MBOX_2_STAT_EN	2	RW	Same as MBOX_3_STAT_EN
MBOX_1_STAT_EN	1	RW	Same as MBOX_3_STAT_EN
MBOX_0_STAT_EN	0	RW	Same as MBOX_3_STAT_EN

MBOX_STAT_INT_STAT_REG

Illustrates current interrupt status of mailboxes.

STAT_INT_STAT_REG is defined once in this document. All other STAT_INT_STAT_REG registers’ definition will be similar to this and their bits will follow their respective STAT_REG.

Card Type: All · FPGA Type: All · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Description
RSVD	31:4	RO	Reserved
MBOX_3_INT_STAT	3	RO	1: MBOX_3 INT is active and requesting service. 0: MBOX_3 INT is inactive.
MBOX_2_INT_STAT	2	RO	Same as MBOX_3_INT_STAT
MBOX_1_INT_STAT	1	RO	Same as MBOX_3_INT_STAT
MBOX_0_INT_STAT	0	RO	Same as MBOX_3_INT_STAT

MBOX_STAT_INT_CLR_REG

Write one in this register to clear respective interrupt in MBOX_STAT_INT_STAT_REG. Applicable to Edge Interrupts.

STAT_INT_CLR_REG is defined once in this document. All other STAT_INT_CLR_REG registers’ definition will be similar to this and their bits will follow their respective STAT_REG.

Card Type: All · FPGA Type: All · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Description
RSVD	31:4	RO	Reserved
MBOX_3_INT_CLR	3	RW	One in this bit location clears MBOX_3_INT_STAT. This bit resets itself in next clock cycle after a one is written into it, so it will always show 0 if SW attempt to read it.
MBOX_2_INT_CLR	2	RW	Same as MBOX_3_INT_CLR
MBOX_1_INT_CLR	1	RW	Same as MBOX_3_INT_CLR
MBOX_0_INT_CLR	0	RW	Same as MBOX_3_INT_CLR

SCRTCH_n_REG

Card Type: All · FPGA Type: All · Function: All · POR Value: 0x0000_0000

Scratch Pad

Field	Bits	Type	Reset	Description
DATA	31:0	RW	0

SEM_REG

Here is how SEM_REG works:

If the content of this register is zero, then it will allow SW to write any value on that.
If the content of this register is nonzero, then SW is not allowed to write any value in this register but SW can clear this register by writing zero in it. In other words since this is 8-bit register, SW can clear this register by writing any value which has bits [7:0] = 8’h00. SW can always write zero in this register. Card Type: All · FPGA Type: All · Function: All · POR Value: 0x0000_0000

Semaphore

Field	Bits	Type	Reset	Description
RSVD	31:8	RO	All 0s	Reserved
DATA	7:0	RW	0

SPI_CMD_STAT_REG

SW should set only single command bit at a time. If more than one command bits are set, only the command bit in lower bit position will be executed. For example of READ_DW and WRITE_DW commands are set, only READ_DW (which is in lower bit position) is executed.

Card Type: ALL · FPGA Type: CB · Function: 2 · POR Value: 0x0000_0100

Instruct FPGA to erase, read from, and write into SPI peripheral.

Field	Bits	Type	Reset	Description
INT_EN	31	RW	0	1: Interrupt Enabled.
RSVD	30:12	RO	0	Reserved
INT	11	W1C	0	1: SPI transaction is completed.
ILLEGAL_ERASE	10	W1C	0	1: ILLEGAL ERASE detected. Trying to erase a protected sector. In Virtual SPI Reg: Not Used.
ILLEGAL_WRITE	9	W1C	0	1: ILLEGAL WRITE detected. Trying to write in a protected sector. In Virtual SPI Reg: Not Used.
READY	8	RO	1	1: Flash memory controller is ready and can accept new command. 0: Flash memory controller is executing a command and cannot accept new command. Recommendation: SW should check this bit before initiating a new command.
READ_ID	7	RW	0	1: Read Device Identification from the memory device 0: No Action This bit is not used for internal flash access in PMC, ICB-FT and ICB-RDC FPGAs. In Virtual SPI Reg: Not Used.
READ_SILICON_ID	6	RW	0	Not used in Ridley. Use bit 7 to read silicon ID.
READ_STATUS	5	RW	0	This is to read Status Register-1 from flash. This bit is used differently in VSPI flash. In Virtual SPI Flash this bit is W1C. 1: Read Failed 0: Read Successful In Virtual SPI Reg this bit is not used.
PROTECT_SECTOR	4	RW	0	Not used in Ridley.
ERASE_SECTOR	3	RW	0	1: Erase a sector specified by SPI_ADD_REG. 0: No Action In Virtual SPI Reg: Not Used.
WRITE_W	2	RW	0	1: Write one DW in Flash Memory address specified by SPI_ADD_REG. The data to be written should be stored in SPI_WR_DATA_REG. 0: No Action
READ_W	1	RW	0	1: Read one DW from address specified by SPI_ADD_REG. The read data will be stored in SPI_RD_DATA_REG. 0: No Action
NEW_COMMAND	0	RW	0	1: The command specified in Bit1 to 7 is a new command. 0: Command has been executed by FPGA and if there is any command bit set, FPGA will assume it is old command and will ignore it. To initiate a new command (specified by bit1 to bit7), SW should set NEW_COMMAND bit high. This bit is de-asserted by FPGA after command is executed. For Virtual SPI, if SW trigger a SPI command and the NEW_COMMAND bit never get cleared by FPGA (due to errors on the LSB bus) then SW can clear NEW_COMMAND bit and initiate another SPI command. In such a condition,

SPI_ADD_REG

In SPI controller and in VSPI-Flash this register is used as it is defined in the description field below, but in VSPI-WB the upper 4 bits are used differently. In VSPI_WB, this register is used to specify the address of the register in the remote FPGA. Bits [19:0] are used as register offset (relative address in the respective function). Bits [23:20] are used to specify the function.

Bits [23:20] = 0x1 and 0x0 specifies function 0.

Bits [23:20] = 0x2 specifies function 1.

Bits [23:20] = 0x4 specifies function 2.

Bits [23:20] = 0x8 specifies function 3.

Other values for Bits[23:20] are invalid.

Card Type: ALL · FPGA Type: CB · Function: 2 · POR Value: 0x0000_0000

Specifies an address in SPI Peripheral

Field	Bits	Type	Reset	Description
RSVD	31:24	RO	0	Reserved
ADDR	23:0	RW	0	This field specifies the word address for READ_DW and WRITE_DW operation. A valid word address should have two LSB bits of zero. For sector erase command, the address placed in this field can be any valid address in the sector that you can erase.

SPI_WR_DATA_REG

Card Type: ALL · FPGA Type: CB · Function: 2 · POR Value: 0x0000_0000

Data to be written in SPI Peripheral.

Field	Bits	Type	Reset	Description
WR_DATA	31:0	RW	0	32-bit data to be written in Configuration Flash Memory.

SPI_RD_DATA_REG

Card Type: ALL · FPGA Type: CB · Function: 2 · POR Value: 0x0000_0000

Data read from SPI Peripheral

Field	Bits	Type	Reset	Description
RD_DATA	31:0	RO	0	FPGA stores read data from configuration flash memory in this register. The register content is valid after Read command is executed and will remain valid before the next command starts, so SW is expected to read this register after read command executed before issuing another command.

SPI_RST_REG

Card Type: ALL · FPGA Type: CB · Function: 2 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:4	RO	0
LCL_RST	3:0	RW	0	0xD: Reset the local SPI controller or local VSPI module. With reset all registers are initialized by their POR value. All state machines are initialized to their initial state. After successful reset of SPI controller, this register will also be cleared to zero. Any other values other than 0xD will be ignored by FPGA.

I2C_PRSCL_LO_REG

Pre-scale value is calculated as: [(input clock HZ) / (5xdesired SCL HZ)] – 1.

Below values have been calculated based on 75MHZ input clock.

Pre-scale = 0x88 (136 decimal) for 100KHZ SCL

Pre-scale = 0x24 (36 decimal) for 400KHZ SCL

Change the value of the prescale register only when the I2C_MOD_EN bit is cleared.

Card Type: ALL · FPGA Type: ALL · Function: 3, none · POR Value: 0x0000_00FF

This register is used to pre-scale the SCL clock line

Field	Bits	Type	Reset	Description
RSVD	31:8	RO	All 0s	Reserved
PRESCALE	7:0	RW	0xFF	Clock Pre scale register lo-byte

I2C_PRSCL_HI_REG

Card Type: ALL · FPGA Type: ALL · Function: 3, none · POR Value: 0x0000_00FF

This register is used to pre-scale the SCL clock line

Field	Bits	Type	Reset	Description
RSVD	31:8	RO	All 0s	Reserved
PRESCALE	7:0	RW	0xFF	Clock Pre scale register hi-byte

I2C_CTRL_REG

Card Type: ALL · FPGA Type: ALL · Function: 3, none · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:8	RO	All 0s	Reserved
I2C_MOD_EN	7	RW	0	“1” means core is enabled. “0” means core is disabled.
I2C_MOD_INT_EN	6	RW	0	“1” means interrupt is enabled. “0” means interrupt is disabled.
RSVD	5:0	RO	0	Reserved

I2C_TX_REG

This is Transmit Register during register write operation but it will be Receive Register during register read operation.

Card Type: ALL · FPGA Type: ALL · Function: 3, none · POR Value: 0x0000_0000

Transmit Data Register

Field	Bits	Type	Reset	Description
RSVD	31:8	RO	All 0s	Reserved
DATA_BYTE_TX	7:0	WO	0x0	Next byte to be transmitted by I2C. In case of data transfer, bit [0] represents the data’s LSB. In case of a slave address transfer bit [0] represents the RW bit. ‘1’ means reading from slave and ‘0’ means writing to slave.

I2C_RX_REG

Card Type: ALL · FPGA Type: ALL · Function: 3, none · POR Value: 0x0000_0000

Receive Data Register

Field	Bits	Type	Reset	Description
RSVD	31:8	RO	All 0s	Reserved
DATA_BYTE_RX	7:0	RO	0x00	Last byte received via I2C

I2C_CMD_REG

This is command register during register write operation. During register read it will be status register.

Command bits [0] and [4:7] are cleared when I2C byte transaction is done or when bus arbitration is lost.

Prior to setting a command SW has to make sure right values have already been written in pre‐scale, Ctrl, Mux, and TX registers

Card Type: ALL · FPGA Type: ALL · Function: 3, none · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:8	RO	All 0s	Reserved
STA	7	WO	0	generate (repeated) start condition
STO	6	WO	0	generate stop condition
RD	5	WO	0	read from slave
WR	4	WO	0	write to slave
ACK	3	WO	0	when a receiver, sent ACK (ACK = ‘0’) or NACK (ACK = ‘1’)
RSVD	2:1	RO	0	Reserved
INT_ACK	0	WO	0	Interrupt acknowledge. When set, clears a pending interrupt.

I2C_STAT_REG

Card Type: ALL · FPGA Type: ALL · Function: 3, none · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:8	RO	All 0s	Reserved
RX_ACK	7	RO	0	Received acknowledge from slave. This flag represents acknowledge from the addressed slave. ‘1’ = No acknowledge received ‘0’ = Acknowledge received
BUSY	6	RO	0	I2C bus busy ‘1’ after START signal detected ‘0’ after STOP signal detected
ARB_LOST	5	RO	0	Arbitration lost. This bit is set when the core lost arbitration. Arbitration is lost when: • a STOP signal is detected, but not requested • The master drives SDA high, but SDA is low.
RSVD	4:2	RO	0	write to slave
TIP	1	RO	0	Transfer in progress ‘1’ when transferring data ‘0’ when transfer complete
INT_FLAG	0	RO	0	This bit is set when an interrupt is pending, which will cause a processor interrupt request if the IEN (INT_EN) bit is set. The Interrupt Flag is set when: • one byte transfer has been completed • arbitration is lost

I2C_MUX_SEL_REG

If a single I2C port is used to communicate with multiple I2C devices, then SW needs to set the device number in this register to specify which device it wants to talk to. FPGA will use this register to set the right values for the Enable and Select pins of the external I2C multiplexers.

If there is no external I2C multiplexer connected to I2C controller, value of this register is simply ignored and has no effect in I2C controller functions.

Card Type: ALL · FPGA Type: ALL · Function: 3, none · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:8	RO	0
DEV_SEL	7:0	RW	0	Specifies the I2C device that needs to be connected to I2C controller. FPGA use this value to set the enable and select pins for the external I2C multiplexer.

I2C_RST_REG

Card Type: ALL · FPGA Type: ALL · Function: 3, none · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:4	RO	0
LCL_RST	3:0	RW	0	0xD: Reset the local I2C controller or local VI2C module. With reset all registers are initialized by their POR value. All state machines are initialized to their initial state. After successful reset of I2C controller, this register will also cleared to zero. Any other values other than 0xD will be ignored by FPGA.

LED_SYNC_REG

Card Type: ALL · FPGA Type: ALL · Function: 0, none · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:1	RO	0
LED_SYNC	0	RW	0	This is used to synchronize the LED blinks on all the boards in chassis. SW write 1 in this bit to synchronize the LEDs. 1: Resets blinking status of all the Leds 0: no Action This bit is automatically cleared by FPGA.

LED_CONFIG_REG

Card Type: ALL · FPGA Type: ALL · Function: 0, none · POR Value: 0x0003_0705

Field	Bits	Type	Reset	Description
RSVD	31:28	RO	0	Reserved
LED_TMR_CTRL	27:24	RW	0	0x09: Turns of the LED timer Other values: no effect. This field is only used at 300 sec after power up or after FPGA reconfiguration. SW has to write 0x9 in this field within 300 sec after power up (or after FPGA reconfiguration) to illustrate that it is in control otherwise FPGA will change the status of HEALTH LED to Orange Slow blink. After FPGA changed the status of HEALTH LED, SW still can change the status of the LED by writing in respective LED control bits in LED control register.
RSVD	23:21	RO	0	Reserved
FST_BLNK_SPD	20:16	RW	0x3	The value of this field is used only if LED is in fast blink mode. 0: 100ms 1: 200ms 3: 400ms … 31: 3200ms (3.2 sec)
RSVD	15:13	RO	0
SLW_BLNK_SPD	12:8	RW	0x7	The value of this field is used only if LED is in slow blink mode. 0: 100ms 1: 200ms 3: 400ms … 31: 3200ms (3.2 sec)
RSVD	7:4	RO	0
BRGHT_LVL	3:0	RW	0x5	The value of this field is used only when we put LED in half-bright mode in LED_CTRL_REG. 0: off 1: 10% of full brightness 2: 20% of full brightness …. 9: 90% of full brightness 10 to 15: Full bright

FPGA_RECONFIG_CTRL_REG

Card Type: All · FPGA Type: All · Function: 0, none · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:9	RO	All 0s	Reserved
SELECT_IMAGE	8	RW	0	0: Boot from App1 1: Boot from App2
UPDATE_FIRST_BOOT	7:4	RW	0	0xD: Update ‘First Boot’ value in the Flash to the value shown by #SELECT_IMAGE Any other value: Does nothing. This field will get cleared by FPGA after command is executed successfully.
START_RECONFIG	3:0	RW	0	0xD: Start FPGA reconfiguration Any other value: Does nothing.

FPGA_RECONFIG_STAT_REG

Card Type: All · FPGA Type: All · Function: 0 · POR Value: 0x0000_0002

Field	Bits	Type	Reset	Description
RSVD	31:5	RO	All 0s	Reserved
ERROR_FIRST_BOOT	4	RO	0	1: Error in UPDATE_FIRST_BOOT command
BUSY	3	RO	0	FPGA reconfiguration is busy and executing a command.
ERROR	2	RO	0	0: No Error in FPGA Configuration 1: Error observed in FPGA reconfiguration
CURRENT_IMAGE	1:0	RO	10	10: App1 11: App2

CB Registers

All registers are not protected by default unless specified.

Function 0

FPGA_REV_ID_REG

FUNC_CAP_0_REG

FPGA_RECONFIG_CTRL_REG

FPGA_RECONFIG_STAT_REG

SCRTCH_n_REG

DEV_MSI_0_PEND_REG (TBD)

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:1	RO	All 0s	Reserved
MBOX_INT	0	RO	0	1: MBOX requires service. 0: no service is requested.

DEV_MSI_0_INT_EN_REG (TBD)

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:1	RO	0	Reserved
MBOX_INT_EN	0	RW	0	1: MBOX interrupt is enabled. 0: MBOX interrupt is disabled.

PWR_CTRL_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0009

Field	Bits	Type	Reset	Description
PWR_SUICIDE	31:16	RW	All 0s	Value of 0xA73D in this register will disable 1Khz signal sent out to the hardware external watchdog and toggle the reconfiguration pin of CB. This field is used for CB post-ISP update.
THERMAL_SUICIDE_SWB_1	15:12	RW	All 0s	0x6: Force SWB 1 PSSM to enter Thermal Fault state, CB will shutdown all power rails and recovers after 5min. SW writes to this register when it detects over-temperature event. Any other value: no effect, FPGA will not take any action. This bit is automatically cleared to 0 after shutdown.
THERMAL_SUICIDE_SWB_0	11:8	RW	All 0s	0x6: Force SWB 0 PSSM to enter Thermal Fault state, CB will shutdown all power rails and recovers after 5min. SW writes to this register when it detects over-temperature event. Any other value: no effect, FPGA will not take any action. This bit is automatically cleared to 0 after shutdown.
THERMAL_SUICIDE_MAIN	7:4	RW	0x0	0x6: Force Main PSSM to enter Thermal Fault state, CB will shutdown all power rails and recovers after 5min. SW writes to this register when it detects over-temperature event. Any other value: no effect, FPGA will not take any action. This bit is automatically cleared to 0 after shutdown.
EN_ISP_MODE	3:0	RW	0x9	0x6: Enter ISP mode. 0x9: Disable ISP mode. Although any value can be written in this field by SW, FPGA will not take action if the value is not 0x6 or 0x9 and will keep the previous Enable/Disable status. When enabled, this disable the power sequence logic of CB from monitoring the power good of PMC, SWB and ICB that is invalid when the PMC, SWB or ICB are performing self-reconfiguration.

PWR_STAT_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:11	RO	All 0s	Reserved
SWB_1_ALL_PG	10	RO	1	1: Pgood is okay
SWB_0_ALL_PG	9	RO	1	1: Pgood is okay
PDB_ALL_PG	8	RO	1	1: Pgood is okay
RSVD	7	RO	0	Reserved
SWB1_PWROK	6	RO	0	Indicates the power sequencing of SWB 1 is completed. 1: Asserted 0: De-asserted
SWB0_PWROK	5	RO	0	Indicates the power sequencing of SWB 0 is completed. 1: Asserted 0: De-asserted
CB_PWROK	4	RO	0	Indicates the power sequencing of Control Board is completed. 1: Asserted 0: De-asserted
RSVD	3:1	RO	0	Reserved
PMC_PWR_INT	0	RO	0	PMC Power interrupt 1: Asserted 0: De-asserted (signal is buffered from PMC)

RS232_SPD_SNS_REG

This register allows the sensing of the console baud rate. A write to this register will reset the counter and arm the speed sense circuit. When a character is sensed, the counter counts to the end of the start bit. At this point an interrupt is set and the count can be read to allow the baud rate to be determined. Upon writing this register back to zero, you clear the interrupt and send the state machine back to the wait for character state.

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

This register allows the sensing of the console baud rate

Field	Bits	Type	Reset	Description
RSVD	31:18	RO	All 0s	Reserved
SPEED_SENSE	17:0	RW	0x00000	Number of clocks the start bit is low. A character with odd ASCII code (e.g. Carriage Return) should be selected for speed sense.

RS232_CLR_SPD_SNS_REG

Speed Sense Interrupt will be reset by writing to this register.

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Clear Speed Sense Interrupt

Field	Bits	Type	Reset	Description
RSVD	31:0	RO		Write any value to clear the Speed Sense Interrupt

TPM_STAT_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:1	RO	All 0s	Reserved
TPM_INT	0	RO	0	1: Request for Service (signal is buffered from PMC)

PMC_CTRL_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:12	RO	All 0s	Reserved
PMC_LSB_RST	11:8	RW	0	Reset control of PMC LSB 0xD: Asserted Any other value: de-asserted. When asserted by SW, will reset the PMC LSB port and all related processors. This Field is automatically cleared by FPGA after reset is issued.
RSVD	7:0	RO	0	Reserved

PMC_STAT_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:28	RO	All 0s	Reserved
LSB_PROC_TYP_ERR	27	RO	0	One of the processors in LSB port received a packet with an invalid value in type field.
LSB_PROC_FATAL_ERR	26	RO	0	One of the state machines in one of the processors in LSB port has gone momentarily to unknown state.
LSB_PROC_EOP_ERR	25	RO	0	One of the processors in LSB port received a packet without EOP.
LSB_PROC_SOP_ERR	24	RO	0	One of the processors in LSB port received a packet without SOP.
RSVD	23:19	RO	0	Reserved
LSB_TX_FATAL_ERR	18	RO	0	One of the state machines in LSB TX PHY has gone momentarily to unknown state.
LSB_TX_EOP_ERR	17	RO	0	LSB TX PHY received a packet without EOP from one of the processors.
LSB_TX_SOP_ERR	16	RO	0	LSB TX PHY received a packet without SOP from one of the processors.
RSVD	15	RO	0	Reserved
LSB_RX_REV_NO_ERR	14	RO	0	REV of the received packet does not match with the REV_NO of the LSB RX PHY.
LSB_RX_UNEXP_ERR	13	RO	0	Unexpected condition in LSB RX PHY. 1: means RX_BUF is almost full or LSB_RX_PHY_CTRL has received a packet without SOP from DES (deserializer)
LSB_RX_SEQNO_ERR	12	RO	0	LSB RX PHY received a packet from remote party with invalid SEQ no.
LSB_RX_DEV_ID_ERR	11	RO	0	LSB RX PHY received a packet from remote party with invalid DEV-ID.
LSB_RX_FATAL_ERR	10	RO	0	One of the state machines in LSB RX PHY has gone momentarily to unknown state.
LSB_RX_LNGTH_ERR	9	RO	0	LSB RX PHY received a packet from remote party with invalid Length.
LSB_RX_CHKSM_ERR	8	RO	0	LSB RX PHY received a packet from remote party with checksum error.
RSVD	7:0	RO	0	Reserved

ICB_CTRL_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:24	RO	All 0s	Reserved
HSC_ENC_LATCH_OFF	23:21	RW	0x0	Send special Encoded Reset to ICB to hotswap controllers LATCH_OFF signal 0xD: Asserted Any other value: de-asserted. When asserted by SW, will power OFF system until switch tray removal. This Field is automatically cleared by FPGA after reset is issued.
HSC_ENC_RST	19:16	RW	0x0	Send special Encoded Reset to ICB to toggle hotswap controllers 0xD: Asserted Any other value: de-asserted. When asserted by SW, will cycle the system power. This Field is automatically cleared by FPGA after reset is issued.
RSVD	15:12	RO	All 0s	Reserved
ICB_LSB_RST	11:8	RW	0x0	Reset control of ICB LSB 0xD: Asserted Any other value: de-asserted. When asserted by SW, will reset the ICB LSB port and all related processors. This Field is automatically cleared by FPGA after reset is issued.
RSVD	7:4	RO	0	Reserved
ICB_ERST	3:0	RW	0	Reset control of ICB 0xD: Asserted Any other value: de-asserted. When asserted by SW, will send encoded reset to the SWB on the respective switch board. The reset will be sent once, when this field is set to 0xD. This Field is automatically cleared by FPGA after encoded reset is issued.

ICB_STAT_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0002

Field	Bits	Type	Reset	Description
RSVD	31:28	RO	All 0s	Reserved
LSB_PROC_TYP_ERR	27	RO	0	One of the processors in LSB port received a packet with an invalid value in type field.
LSB_PROC_FATAL_ERR	26	RO	0	One of the state machines in one of the processors in LSB port has gone momentarily to unknown state.
LSB_PROC_EOP_ERR	25	RO	0	One of the processors in LSB port received a packet without EOP.
LSB_PROC_SOP_ERR	24	RO	0	One of the processors in LSB port received a packet without SOP.
RSVD	23:19	RO	0	Reserved
LSB_TX_FATAL_ERR	18	RO	0	One of the state machines in LSB TX PHY has gone momentarily to unknown state.
LSB_TX_EOP_ERR	17	RO	0	LSB TX PHY received a packet without EOP from one of the processors.
LSB_TX_SOP_ERR	16	RO	0	LSB TX PHY received a packet without SOP from one of the processors.
RSVD	15	RO	0	Reserved
LSB_RX_REV_NO_ERR	14	RO	0	REV of the received packet does not match with the REV_NO of the LSB RX PHY.
LSB_RX_UNEXP_ERR	13	RO	0	Unexpected condition in LSB RX PHY. 1: means RX_BUF is almost full or LSB_RX_PHY_CTRL has received a packet without SOP from DES (deserializer)
LSB_RX_SEQNO_ERR	12	RO	0	LSB RX PHY received a packet from remote party with invalid SEQ no.
LSB_RX_DEV_ID_ERR	11	RO	0	LSB RX PHY received a packet from remote party with invalid DEV-ID.
LSB_RX_FATAL_ERR	10	RO	0	One of the state machines in LSB RX PHY has gone momentarily to unknown state.
LSB_RX_LNGTH_ERR	9	RO	0	LSB RX PHY received a packet from remote party with invalid Length.
LSB_RX_CHKSM_ERR	8	RO	0	LSB RX PHY received a packet from remote party with checksum error.
RSVD	7:3	RO	0	Reserved
ICB_INT	2	RO	0	INT request of PDB board 1: ICB requests interrupt 0: No interrupt requested This bit stores the filtered status of the pin
ICB_RDY	1	RO	1	Ready status of ICB FPGA 1: ICB is Ready 0: ICB is Not Ready This bit stores the filtered status of the pin.
RSVD	1:0	RO	0	Reserved

SWB_CTRL_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:12	RO	All 0s	Reserved
SWB_LSB_RST	11:8	RW	0	Reset control of SWB_FPGA LSB 0xD: Asserted Any other value: de-asserted. When asserted by SW, will reset the SWB_FPGA LSB port and all related processors. This Field is automatically cleared by FPGA after reset is issued.
SWB_PERST	7:4	RW	All 0s	PCIE Reset control of SWB 0xD: Asserted Any other value: De-asserted This Field is NOT automatically cleared by FPGA after reset is issued.
SWB_ERST	3:0	RW	0	Reset control of SWB 0xD: Asserted Any other value: de-asserted. When asserted by SW, will send encoded reset to the SWB on the respective switch board. The reset will be sent once, when this field is set to 0xD. This Field is automatically cleared by FPGA after encoded reset is issued.

SWB_STAT_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0001

Field	Bits	Type	Reset	Description
RSVD	31:28	RO	All 0s	Reserved
LSB_PROC_TYP_ERR	27	RO	0	One of the processors in LSB port received a packet with an invalid value in type field.
LSB_PROC_FATAL_ERR	26	RO	0	One of the state machines in one of the processors in LSB port has gone momentarily to unknown state.
LSB_PROC_EOP_ERR	25	RO	0	One of the processors in LSB port received a packet without EOP.
LSB_PROC_SOP_ERR	24	RO	0	One of the processors in LSB port received a packet without SOP.
RSVD	23:19	RO	0	Reserved
LSB_TX_FATAL_ERR	18	RO	0	One of the state machines in LSB TX PHY has gone momentarily to unknown state.
LSB_TX_EOP_ERR	17	RO	0	LSB TX PHY received a packet without EOP from one of the processors.
LSB_TX_SOP_ERR	16	RO	0	LSB TX PHY received a packet without SOP from one of the processors.
RSVD	15	RO	0	Reserved
LSB_RX_REV_NO_ERR	14	RO	0	REV of the received packet does not match with the REV_NO of the LSB RX PHY.
LSB_RX_UNEXP_ERR	13	RO	0	Unexpected condition in LSB RX PHY. 1: means RX_BUF is almost full or LSB_RX_PHY_CTRL has received a packet without SOP from DES (deserializer)
LSB_RX_SEQNO_ERR	12	RO	0	LSB RX PHY received a packet from remote party with invalid SEQ no.
LSB_RX_DEV_ID_ERR	11	RO	0	LSB RX PHY received a packet from remote party with invalid DEV-ID.
LSB_RX_FATAL_ERR	10	RO	0	One of the state machines in LSB RX PHY has gone momentarily to unknown state.
LSB_RX_LNGTH_ERR	9	RO	0	LSB RX PHY received a packet from remote party with invalid Length.
LSB_RX_CHKSM_ERR	8	RO	0	LSB RX PHY received a packet from remote party with checksum error.
RSVD	7:3	RO	0	Reserved
SWB_INT	2	RO	0	INT request of switch board 1: SWB requests interrupt 0: No interrupt requested This bit stores the filtered status of the pin
RSVD	1	RO	0	Reserved
SWB_PRSNT	0	RO	1	Present status of switch board 1: SWB is present 0: SWB is Not Present This bit stores the filtered status of the pin.

BMC_CTRL_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0160

Field	Bits	Type	Reset	Description
RSVD	31:9	RO	All 0s	Reserved
BMC_BOOT_SEL	8	RW	1	Boot selection for BMC 1: SPI flash 0: UART
BMC_PWR_EN	7:4	RW	0x6	Power control of BMC 0x6: Enable 0x9: Disable Although any value can be written in this field by SW, but FPGA will not take action if the value is not 0x6 or 0x9 and will keep the previous Enable/Disable status.
BMC_RST	3:0	RW	0x0	Reset control of BMC 0xD: Asserted Any other value: de-asserted. When asserted by SW, will reset the BMC module. This Field is automatically cleared by FPGA after reset is issued.

BMC_STAT_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:5	RO	All 0s	Reserved
BMC_WDT_RST	4	RO	0	BMC Watchdog reset 1: Asserted 0: De-asserted
RSVD	3:1	RO	All 0s	Reserved
BMC_PRSNT	0	RO	0	Present status of BMC 1: Present 0: Not present

THRM_STAT_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:7	RO	All 0s	Reserved
TEMP_SNSR_TMP432A_ALERT	6	RO	0	On-board Temp Sensor (TM432A) alert, monitor location A,B and E (see ES for details) 1: Asserted 0: De-asserted
TEMP_SNSR_TMP75_D_ALERT	5	RO	0	On-board Temp Sensor (TMP75) alert, monitor location D (see ES for details) 1: Asserted 0: De-asserted
TEMP_SNSR_TMP75_C_ALERT	4	RO	0	On-board Temp Sensor (TMP75) alert, monitor location C (see ES for details) 1: Asserted 0: De-asserted
RSVD	3:2	RO	All 0s	Reserved
CPU_EXT_TEMP_SNSR_ALERT	1	RO	0	CPU External Temp Sensor (TMP461) alert, monitor CPU local, PMC and SSD temperature 1: Asserted 0: De-asserted (signal is buffered from PMC)
CPU_INT_THRM_TRIP	0	RO	0	CPU over temperature and unconditional shutdown 1: Asserted 0: De-asserted (signal is buffered from PMC)

USB_CTRL_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0006

Field	Bits	Type	Reset	Description
RSVD	31:4	RO	All 0s	Reserved
USB_5V_EN	3:0	RW	0x6	Enable for USB 5V current limit switch 0x6: Enable 0x9: Disable Although any value can be written in this field by SW, but FPGA will not take action if the value is not 0x6 or 0x9 and will keep the previous Enable/Disable status.

USB_STAT_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:2	RO	All 0s	Reserved
USB_VBUS_DET	1	RO	0	1: USB VBUS detected 0: USB VBUS not detected (signal is buffered from PMC)
USB_5V_FAULT	0	RO	0	1: USB 5V fault is asserted 0: USB 5V fault is not asserted (signal is buffered from PMC)

BTN_STAT_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:1	RO	All 0s	Reserved
FP_BTN	0	RO	0	Front Panel button is pressed. 1: Asserted 0: De-asserted

LEAK_STAT_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:2	RO	All 0s	Reserved
LEAK_ALERT	1	RO	0	Leak ADC module Alert 1: Asserted 0: De-asserted
LEAK_ADC_INT	0	RO	0	Leak ADC module Interrupt 1: Interrupt asserted 0: Interrupt de-asserted

NFC_CTRL_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:4	RO	All 0s	Reserved
NFC_EN	3:0	RO	0	Enable (Wake) signal of NFC module 0x6: Enable 0x9: Disable Although any value can be written in this field by SW, but FPGA will not take action if the value is not 0x6 or 0x9 and will keep the previous Enable/Disable status.

NFC_STAT_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0001

Field	Bits	Type	Reset	Description
RSVD	31:3	RO	All 0s	Reserved
NFC_INT	2	RO	0	INT request of NFC module 1: NFC requests interrupt 0: No interrupt requested This bit stores the filtered status of the pin
RSVD	1	RO	0	Reserved
NFC_PRSNT	0	RO	1	Present status of NFC module 1: NFC is present 0: NFC is Not Present This bit stores the filtered status of the pin.

INTRD_STAT_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Intrusion detection status

Field	Bits	Type	Reset	Description
RSVD	31:2	RO	All 0s	Reserved
HANDLE_INT	1	RO	0	Interrupt of tray service or removal intent 1: Interrupt is asserted 0: Interrupt is not asserted
COVER_INT	0	RO	0	Interrupt of top cover 1: Interrupt is asserted 0: Interrupt is not asserted

BTRY_STAT_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:1	RO	All 0s	Reserved
BTRY_UDV_ALERT	0	RO	0	Battery Under-voltage alert 1: Asserted 0: De-asserted

EN_ACCSS_PRTCTD_REG

This register is to protect critical registers from accidental writes. SW should write 0x8F35_D72C in order to have write access to protected registers.

Card Type: All · FPGA Type: PMC · Function: None · POR Value: 0x0000_0000

Enables access to protected registers.

Field	Bits	Type	Reset	Description
EN_ACCSS	31:0	RW	0	0x8F35_D72C: Enables access to protected registers. Other Values: Disables access to protected registers.

UART_MUX_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:26	RO	All 0s	Reserved
SWB1_MUX_SEL	25:24	RW	0x0	SWB1 MUX select 3: UART Channel 4 2: UART Channel 3 1: UART Channel 2 0: UART Channel 1
RSVD	23:22	RO	All 0s	Reserved
SWB0_MUX_SEL	21:20	RW	0x0	SWB0 MUX select 3: UART Channel 4 2: UART Channel 3 1: UART Channel 2 0: UART Channel 1
RSVD	19:18	RO	All 0s	Reserved
BMC_MUX_SEL	17:16	RW	0x0	BMC MUX select 2: SWB1 1: SWB0 0: USB Console
RSVD	15:14	RO	All 0s	Reserved
CPU_DBG_MUX_SEL	13:12	RW	0x0	CPU Debug MUX select 2: SWB1 1: SWB0 0: USB Console
RSVD	11:10	RO	All 0s	Reserved
CPU_CNSL_MUX_SEL	9:8	RW	0x0	CPU Console MUX select 2: SWB1 1: SWB0 0: USB Console
RSVD	7:5	RO	All 0s	Reserved
USB_CNSL_MUX_SEL	4:0	RW	0x0	USB Console MUX select 4: SWB1 3: SWB0 2: BMC 1: CPU Debug 0: CPU Console

I2C_MUX_RST_REG

Card Type: All · FPGA Type: CB · Function: none · POR Value: 0x0000_00DD

Field	Bits	Type	Reset	Description
RSVD	31:8	RO	All 0s	Reserved
I2C_CH14_MUX_RST	7:4	RW	0xD	Reset control of I2C CH14 MUX 0xD: Asserted Any other value: de-asserted. This Field is NOT automatically cleared by FPGA after reset is issued.
I2C_CH10_MUX_RST	3:0	RW	0xD	Reset control of I2C CH10 MUX 0xD: Asserted Any other value: de-asserted. This Field is NOT automatically cleared by FPGA after reset is issued.

CPU_INTR_CTRL_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:2	RO	All 0s	Reserved
CPU_INTR_2	1	RW	0	Control interrupt 2 to CPU 1: Assert interrupt 0: De-assert interrupt
CPU_INTR_1	0	RW	0	Control interrupt 1 to CPU 1: Assert interrupt 0: De-assert interrupt

BMC_JTAG_CTRL_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Controls the source to/fom JTAG pins of BMC

Field	Bits	Type	Reset	Description
RSVD	31:8	RO	All 0s	Reserved
TDO	7	RO	0	Input, Connected to BMC TDO pin
TDI	6	RW	0	Output Connected to BMC TDI pin
TMS	5	RW	0	Output Connected to BMC TMS pin
TCK	4	RW	0	Output Connected to BMC TCK pin
RSVD	3:1	RO	All 0s	Reserved
JTAG_SEL	0	RW	0	Select the source to BMC JTAG 0: On-board JTAG header 1: CB control with bit [6:4]

SWB_JTAG_CTRL_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0100

Controls the source to/fom JTAG pins of SWB

Field	Bits	Type	Reset	Description
RSVD	31:9	RO	All 0s	Reserved
TRST	8	RW	1	Output Connected to SWB TRST pin
TDO	7	RO	0	Input, Connected to SWB TDO pin
TDI	6	RW	0	Output Connected to SWB TDI pin
TMS	5	RW	0	Output Connected to SWB TMS pin
TCK	4	RW	0	Output Connected to SWB TCK pin
RSVD	3:0	RO	All 0s	Reserved

FLSH_CTRL_REG

This register is clear under two conditions only.

Upon assertion of global reset.
Power cycle Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:12	RO	All 0s	Reserved
PHY2_RETIMER_WP	11	RW	0	PHY Retimer Write Protect 1: Protected, Once asserted, cannot be de-asserted by SW.
PHY2_I210_CTRLR_SPI_WP	10	RW	0	PHY I210 Ethernet Controller SPI Write Protect 1: Protected, Once asserted, cannot be de-asserted by SW.
PHY1_84991_WP	9	RW	0	PHY 84991 Write Protect 1: Protected, Once asserted, cannot be de-asserted by SW.
BMC_EEPRM_WP	8	RW	0	BMC EEPROM Write Protect 1: Protected, Once asserted, cannot be de-asserted by SW.
RSVD	7:3	RO	All 0s	Reserved
ZEROIZATION_WP	2	RW	0	1: Protected, Once asserted, cannot be de-asserted by SW. SW writes into this register bit during boot and use it as a gate for zeroization. This would block a user from running zeroization (or parts of it) in Service-OS and Product-OS. It also blocks them clearing a sticky bit.
FPGA_FLSH_WP	1	RW	0	FPGA (CB) Flash Write Protect 1: Protected, Once asserted, FPGA will not issue any write/erase command to the flash. Once asserted, cannot be de-asserted by SW.
CHSS_EEPRM_WP	0	RW	0	System Key EEPROM Write Protect 1: Protected, Once asserted, cannot be de-asserted by SW.

LED_SYNC_REG

LED_CONFIG_REG

LED_CTRL_0_REG

For bit definitions please refer to the section “LED Control bits”.

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:24	RO	All 0s	Reserved
UID	23:16	RW	0x0	Locator LED
ALM_STAT	15:8	RW	0x0	Alarm status LED
SYS_STAT	7:0	RW	0x0	System status LED

LED_CTRL_1_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:8	RO	All 0s	Reserved
PSU_STAT	7:0	RW	0x0	Fan status LED

LED_CTRL_2_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:8	RO	All 0s	Reserved
FAN_STAT	7:0	RW	0x0	Fan status LED

LED_CTRL_3_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:8	RO	All 0s	Reserved
LEAK_STAT	7:0	RW	0x0	LEAK status LED

LED_CTRL_4_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:16	RO	All 0s	Reserved
PHY_84991_ACT_STAT	15:8	RW	0x0	PHY 84991 activity status bit [7:6] option available (see Chapter 5): 00 = SW control 01 = PHY 84991 LED 0 driver 10 = PHY 84991 LED 1 driver 11 = PHY 84991 LED 2 driver
PHY_84991_LINK_STAT	7:0	RW	0x0	PHY 84991 link status bit [7:6] option available (see Chapter 5): 00 = SW control 01 = PHY 84991 LED 0 driver 10 = PHY 84991 LED 1 driver 11 = PHY 84991 LED 2 driver

LED_CTRL_5_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:16	RO	All 0s	Reserved
PHY_I210_ACT_STAT	15:8	RW	0x0	PHY I210 activity status bit [7:6] option available (see Chapter 5): 00 = SW control 01 = PHY I210 LED 0 driver 10 = PHY I210 LED 1 driver 11 = PHY I210 LED 2 driver
PHY_I210_LINK_STAT	7:0	RW	0x0	PHY I210 link status bit [7:6] option available (see Chapter 5): 00 = SW control 01 = PHY I210 LED 0 driver 10 = PHY I210 LED 1 driver 11 = PHY I210 LED 2 driver

WDG_CTRL_REG

This register will be reset upon CPU POR reset.

Card Type: All · FPGA Type: CB · Function: none · POR Value: 0x3000_0FFF

Watchdog control register

Field	Bits	Type	Reset	Description
WDG_INT_EN	31	RW	0	1: Enables wdog interrupt. 0: Disables wdog interrupt.
WDG_EN	30:27	RW	0x6	0x6: Enables wdog counter. 0x9: Disables wdog counter. Although any value can be written in this field by SW, but FPGA will not take action if the value is not 0x6 or 0x9 and will keep the previous on/off status. After CPU POR reset is asserted, the wdog counter enable status follows the behavior below: POR value when the register bit WDG_EN_POR_MSK of TND_CTRL_REG is de-asserted. Register bit WDG_EN when the WDG_EN_POR_MSK of TND_CTRL_REG is asserted. CPU POR reset will be asserted if WDG_EN is asserted and WDG_CNTR_VALUE = WDG_LNGTH
RSVD	26:12	RO	0	Reserved
WDG_LNGTH	11:0	RW	0xFFF	Number of 100ms ticks before the watchdog triggers. FPGA will never allow 0x000 to be written in this field. If SW tries write 0x000 in this field, FPGA will write POR value in this register. Count Time (ms) 0x0 illegal value 0x1 100.0 0x2 200.0 ... ...

WDG_STAT_REG

Card Type: All · FPGA Type: CB · Function: none · POR Value: 0x0000_0000

Watchdog status register

Field	Bits	Type	Description
WDG_INT	31	RO	1: Asserted, wdog interrupt occurred. 0: De-asserted, no interrupt yet. WDG_INT will be asserted if WDG_INT_EN is asserted and WDG_CNTR_VALUE = WDG_LNGTH
RSVD	30:12	RO	Reserved
WDG_CNTR_VLUE	11:0	RO	Illustrates the current value of wdog counter. Watchdog counter value will keep incrementing if WDG_EN is asserted. Watchdog counter will stop incrementing if counter value gets equal to WDG_LNGTH. Watchdog counter will reset to zero if WDG_EN bit is de-asserted or CPU POR reset is asserted.

WDG_RST_REG

Any write to this register will reset the watchdog counter and de-assert the interrupt.

Card Type: All · FPGA Type: CB · Function: none · POR Value: 0x0000_0000

Watchdog reset register

Field	Bits	Type	Reset	Description
RSVD	31:0	RO	0	Reserved

TND_CTRL_REG

TND_STAT_REG

TND_PWR_CTRL_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_01FF

Field	Bits	Type	Reset	Description
RSVD	31:21	RO	All 0s	Reserved
PSSM_DBG_PIN_OVR	20	RW	0	Enable override of PSSM for all bits [14:2] below 1: Enable 0: Disable
RSVD	19:17	RO	0	Reserved
PSSM_PWR_EN_OVR	16	RW	0	Enable override of PSSM for all bits [8:0] below 1: Enable 0: Disable
RSVD	15	RO	0	Reserved
SWB1_BYPASSBOOT	14	RW	0	SWB1 Bypass Boot value
SWB0_BYPASSBOOT	13	RW	0	SWB0 Bypass Boot value
DBGBOOT	12	RW	0	Debugboot value
RSVD	11:9	RO	All 0s	Reserved
SWB1_PWREN	8	RW	1
SWB1_STBYEN	7	RW	1
SWB0_PWREN	6	RW	1
SWB0_STBYEN	5	RW	1
PHY2_1V8_PWREN	4	RW	1
PHY2_0V8_AVDD_PWREN	3	RW	1
PHY2_0V8_DVDD_PWREN	2	RW	1
PHY_V3P3_PWREN	1	RW	1
CPU_MDL_PWREN	0	RW	1	Power enable overrides 1: Enable 0: Disable

TND_PWR_STAT_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_01FF

Field	Bits	Type	Reset	Description
RSVD	31:19	RO	All 0s	Reserved
DIP_SWB1_BYPASSBOOT	18	RO	0	SWB1 Bypass Boot DIP switch position
DIP_SWB0_BYPASSBOOT	17	RO	0	SWB0 Bypass Boot DIP switch position
DIP_DBGBOOT	16	RO	0	Debugboot DIP switch position
RSVD	15:9	RO	All 0s	Reserved
SWB1_ALL_PG	8	RO	1
SWB1_STBY_PG	7	RO	1
SWB0_ALL_PG	6	RO	1
SWB0_STBY_PG	5	RO	1
PHY2_1V8_PG	4	RO	1
PHY2_0V8_AVDD_PG	3	RO	1
PHY2_0V8_DVDD_PG	2	RO	1
PHY_0V8_AVDD_PG	1	RO	1
CPU_MDL_PG	0	RO	1	Pgood status

TND_CLK_CTRL_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0006_6066

Field	Bits	Type	Reset	Description
RSVD	31:20	RO	All 0s	Reserved
BUF2_En1	19:16	RW	0x6	Clock Buffer 2 Output Enable 1
BUF2_En0	15:12	RW	0x6	Clock Buffer 2 Output Enable 0
RSVD	11:8	RO	All 0s	Reserved
BUF1_En1	7:4	RW	0x6	Clock Buffer 1 Output Enable 1
BUF1_En0	3:0	RW	0x6	Clock Buffer 1 Output Enable 0 0x6: Enable 0x9: Disable Although any value can be written in this field by SW, but FPGA will not take action if the value is not 0x6 or 0x9 and will keep the previous Enable/Disable status.

TND_PMC_GPIO_CTRL_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Description
RSVD	31:15	RO	Reserved
GPI_14	14	RW
GPI_13	13	RW
GPI_12	12	RW
GPI_11	11	RW
GPI_10	10	RW
GPI_9	9	RW
GPI_8	8	RW
GPI_7	7	RW
GPI_6	6	RW
GPI_5	5	RW	1: Assert GPIO 5 0: De-assert GPIO 5
RSVD	4:0	RO	Reserved

TND_PMC_GPIO_STAT_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:5	RO	All 0s	Reserved
GPO_14	14	RO	0
GPO_13	13	RO	0
GPO_12	12	RO	0
GPO_11	11	RO	0
GPO_10	10	RO	0
GPO_9	9	RO	0
GPO_8	8	RO	0
GPO_7	7	RO	0
GPO_6	6	RO	0
GPO_5	5	RO	0	1: GPIO 5 is asserted 0: GPIO 5 is de-asserted
RSVD	4:0	RO	All 0s	Reserved

TND_PMC_GPIO_DIR_CTRL_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Description
RSVD	31:15	RO	Reserved
GPIO_DIR_14	14	RW
GPIO_DIR_13	13	RW
GPIO_DIR_12	12	RW
GPIO_DIR_11	11	RW
GPIO_DIR_10	10	RW
GPIO_DIR_9	9	RW
GPIO_DIR_8	8	RW
GPIO_DIR_7	7	RW
GPIO_DIR_6	6	RW
GPIO_DIR_5	5	RW	1: Indicate GPIO 5 is configured as output and register GPIO_CTRL_REG is used to control this output port value. 0: Indicate GPIO 5 is configured as input and register GPIO_STAT_REG store this input port value.
RSVD	4:0	RO	Reserved

TND_BMC_GPIO_CTRL_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Description
RSVD	31:7	RO	Reserved
GPI_6	6	RW
GPI_5	5	RW
GPI_4	4	RW
GPI_3	3	RW
GPI_2	2	RW
RSVD	1	RO	Reserved
GPI_0	0	RW	1: Assert GPIO 0 0: De-assert GPIO 0

TND_BMC_GPIO_STAT_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:7	RO	All 0s	Reserved
GPO_6	6	RO	0
GPO_5	5	RO	0
GPO_4	4	RO	0
GPO_3	3	RO	0
GPO_2	2	RO	0
RSVD	1	RO	0	Reserved
GPO_0	0	RO	0	1: GPIO 0 is asserted 0: GPIO 0 is de-asserted

TND_BMC_GPIO_DIR_CTRL_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Description
RSVD	31:7	RO	Reserved
GPIO_DIR_6	6	RW
GPIO_DIR_5	5	RW
GPIO_DIR_4	4	RW
GPIO_DIR_3	3	RW
GPIO_DIR_2	2	RW
RSVD	1	RO	Reserved
GPIO_DIR_0	0	RW	1: Indicate GPIO 0 is configured as output and register GPIO_CTRL_REG is used to control this output port value. 0: Indicate GPIO 0 is configured as input and register GPIO_STAT_REG store this input port value.

TND_SWB_GPIO_CTRL_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Description
RSVD	31:8	RO	Reserved
GPI_7	7	RW
GPI_6	6	RW	1: Assert GPIO 6 0: De-assert GPIO 6
RSVD	5:0	RO	Reserved

TND_SWB_GPIO_STAT_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:8	RO	All 0s	Reserved
GPO_7	7	RO	0
GPO_6	6	RO	0	1: GPIO 6 is asserted 0: GPIO 6 is de-asserted
RSVD	5:0	RO	0	Reserved

TND_SWB_GPIO_DIR_CTRL_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Description
RSVD	31:8	RO	Reserved
GPIO_DIR_7	7	RW
GPIO_DIR_6	6	RW	1: Indicate GPIO 6 is configured as output and register GPIO_CTRL_REG is used to control this output port value. 0: Indicate GPIO 6 is configured as input and register GPIO_STAT_REG store this input port value.
RSVD	5:0	RO	Reserved

TND_ICB_GPIO_CTRL_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Description
RSVD	31:4	RO	Reserved
GPI_3	3	RW
GPI_2	2	RW
GPI_1	1	RW	1: Assert GPIO 1 0: De-assert GPIO 1
RSVD	0	RO	Reserved

TND_ICB_GPIO_STAT_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:4	RO	All 0s	Reserved
GPO_3	3	RO	0
GPO_2	2	RO	0
GPO_1	1	RO	0	1: GPIO 1 is asserted 0: GPIO 1 is de-asserted
RSVD	0	RO	0	Reserved

TND_ICB_GPIO_DIR_CTRL_REG

Card Type: All · FPGA Type: CB · Function: 0 · POR Value: 0x0000_0000

Field	Bits	Type	Description
RSVD	31:4	RO	Reserved
GPIO_DIR_3	3	RW
GPIO_DIR_2	2	RW
GPIO_DIR_1	1	RW	1: Indicate GPIO 1 is configured as output and register GPIO_CTRL_REG is used to control this output port value. 0: Indicate GPIO 1 is configured as input and register GPIO_STAT_REG store this input port value.
RSVD	0	RO	Reserved

RST_CAUSE_REG

This is a protected register. This is sticky and does not get reset under global reset condition.

Card Type: All · FPGA Type: CB · Function: None · POR Value: 0x0000_0001

Monitor the main PSSM

Field	Bits	Type	Reset	Description
SW_RST_COOKIES	31:16	RW	All 0s	For SW to read and write.
RSVD	15:9	RO	All 0s	Reserved.
CLD_RST	8	W1C	0	This bit will be set if the System PGOOD is de-sserted from a good state.
RSVD	7:4	RO	All 0s	Reserved.
HW_THERM_RST	3	W1C	0	This bit will be set if the hardware thermal suicide is caused by CB.
WDG_RST	2	W1C	0	This bit will be set if the CB internal watch dog timer is expired.
SW_THERM_RST	1	W1C	0	This bit will be set when SW asserts thermal suicide by asserting #THERMAL_SUICIDE_MAIN field in PWR_CTRL_REG.
PWR_ON_RST	0	W1C	1

RST_CAUSE_SWB_REG

This is a protected register. This is sticky and does not get reset under global reset condition.

Card Type: All · FPGA Type: CB · Function: None · POR Value: 0x0000_0001

Monitor the SWB PSSM

Field	Bits	Type	Reset	Description
SW_RST_COOKIES	31:16	RW	All 0s	For SW to read and write.
RSVD	15:9	RO	All 0s	Reserved.
CLD_RST	8	W1C	0	This bit will be set if the SWB PGOOD is de-sserted from a good state.
RSVD	7:4	RO	All 0s	Reserved.
HW_THERM_RST	3	W1C	0	This bit will be set if the hardware thermal suicide is caused by SWB.
RSVD	2	RO	0	Reserved.
SW_THERM_RST	1	W1C	0	This bit will be set when SW asserts thermal suicide by asserting #THERMAL_SUICIDE_SWB_<SWB_NO> field in PWR_CTRL_REG.
PWR_ON_RST	0	W1C	1

Function 1

FPGA_REV_ID_REG

FUNC_CAP_0_REG

SCRTCH_n_REG

DEV_MSI_0_PEND_REG (TBD)

Card Type: All · FPGA Type: CB · Function: 1 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:1	RO	All 0s	Reserved
MBOX_INT	0	RO	0	1: MBOX requires service. 0: no service is requested.

DEV_MSI_0_INT_EN_REG (TBD)

Card Type: All · FPGA Type: CB · Function: 1 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:1	RO	0	Reserved
MBOX_INT_EN	0	RW	0	1: MBOX interrupt is enabled. 0: MBOX interrupt is disabled.

FAN_CTRL_REG

Card Type: All · FPGA Type: CB · Function: 1 · POR Value: 0x0000_0666

Field	Bits	Type	Reset	Description
RSVD	31:17	RO	All 0s	Reserved
ALL_FAN_FULL_SPD	16	RW	0	Control all Fans (1,2,3) to run at full speed 1: Full speed 0: Non full speed
RSVD	15:12	RW	0x0	Reserved
EFUSE_EN_FAN3	11:8	RW	0x6	Enable of Fan3 EFUSE 0x6: Enable 0x9: Disable Although any value can be written in this field by SW, but FPGA will not take action if the value is not 0x6 or 0x9 and will keep the previous Enable/Disable status.
EFUSE_EN_FAN2	7:4	RW	0x6	Enable of Fan2 EFUSE 0x6: Enable 0x9: Disable Although any value can be written in this field by SW, but FPGA will not take action if the value is not 0x6 or 0x9 and will keep the previous Enable/Disable status.
EFUSE_EN_FAN1	3:0	RW	0x6	Enable of Fan1 EFUSE 0x6: Enable 0x9: Disable Although any value can be written in this field by SW, but FPGA will not take action if the value is not 0x6 or 0x9 and will keep the previous Enable/Disable status.

FAN_STAT_REG

Card Type: All · FPGA Type: CB · Function: 1 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:13	RO	All 0s	Reserved
FAN_CTRLR_ALERT	12	RO	0	Fan controller alert 1: Asserted 0: De-asserted
RSVD	11	RO	0	Reserved
ALRT_FAN_3	10	RO	0	EFUSE alert of Fan 3 1: Asserted 0: De-asserted
ALRT_FAN_2	9	RO	0	EFUSE alert of Fan 2 1: Asserted 0: De-asserted
ALRT_FAN_1	8	RO	0	EFUSE alert of Fan 1 1: Asserted 0: De-asserted
RSVD	7	RO	0	Reserved
PG_FAN_3	6	RO	0	Power status of Fan 3 1: Ok 0: Not Ok
PG_FAN_2	5	RO	0	Power status of Fan 2 1: Ok 0: Not Ok
PG_FAN_1	4	RO	0	Power status of Fan 1 1: Ok 0: Not Ok
RSVD	3	RO	0	Reserved
PRSNT_FAN_3	2	RO	0	Present status of Fan 3 1: Present 0: Not present This bit stores the filtered status of the pin.
PRSNT_FAN_2	1	RO	0	Present status of Fan 2 1: Present 0: Not present This bit stores the filtered status of the pin.
PRSNT_FAN_1	0	RO	0	Present status of Fan 1 1: Present 0: Not present This bit stores the filtered status of the pin.

RTM_CTRL_REG

Card Type: All · FPGA Type: CB · Function: 1 · POR Value: 0x0001_009D

Field	Bits	Type	Reset	Description
RSVD	31:17	RO	All 0s	Reserved
RTM_SERBOOT	16	RW	1	Enable of Serial Boot of Retimer 1: from SPI ROM 0: from MDIO
RSVD	15:8	RO	All 0s	Reserved
RTM_OSC_EN	7:4	RW	0x9	Enable of PHY 81381 retimer 156.25MHz clock 0x6: Enable 0x9: Disable Although any value can be written in this field by SW, but FPGA will not take action if the value is not 0x6 or 0x9 and will keep the previous Enable/Disable status.
RTM_RST	3:0	RW	0xD	Reset of PHY 81381 retimer 0xD: Asserted Any other value: de-asserted. This Field is automatically cleared by FPGA after reset is issued.

RTM_STAT_REG

Card Type: All · FPGA Type: CB · Function: 1 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:1	RO	All 0s	Reserved
PHY_RTM_INT	0	RO	0	Interrupt of PHY 813881 retimer 1: Asserted 0: De-asserted

ETH_CTRLR_CTRL_REG

Card Type: All · FPGA Type: CB · Function: 1 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:3	RO	All 0s	Reserved
SD_PIN2	2	RW	0x0	SW defined output pin2 to I210 controller
SD_PIN1	1	RW	0x0	SW defined output pin1 to I210 controller
SD_PIN0	0	RW	0x0	SW defined output pin0 to I210 controller

ETH_CTRLR_STAT_REG

Card Type: All · FPGA Type: CB · Function: 1 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:2	RO	All 0s	Reserved
I210_WAKE_INT	1	RO	0	‘Wake’ signal from I210 1: Asserted 0: De-asserted
I210_ALRT_INT	0	RO	0	Alert from I210 1: Asserted 0: De-asserted

USRPRT_PWR_CTRL_REG

Card Type: All · FPGA Type: CB · Function: 1 · POR Value: 0x0000_0099

Field	Bits	Type	Reset	Description
RSVD	31:8	RO	All 0s	Reserved
USRPRT_EFUSE_EN_P2	7:4	RW	0x9	Enable EFUSE for UserPort 2 0x6: Enable 0x9: Disable Although any value can be written in this field by SW, but FPGA will not take action if the value is not 0x6 or 0x9 and will keep the previous Enable/Disable status.
USRPRT_EFUSE_EN_P1	3:0	RW	0x9	Enable EFUSE for UserPort 1 0x6: Enable 0x9: Disable Although any value can be written in this field by SW, but FPGA will not take action if the value is not 0x6 or 0x9 and will keep the previous Enable/Disable status.

USRPRT_PWR_STAT_REG

Card Type: All · FPGA Type: CB · Function: 1 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:2	RO	All 0s	Reserved
EFUSE_PG_P2	1	RO	0	EFUSE Pgood of UserPort 2 (QSFP) 1: Asserted 0: De-asserted
EFUSE_PG_P1	0	RO	0	EFUSE Pgood of UserPort 1 (QSFP) 1: Asserted 0: De-asserted

USRPRT_CTRL_0_REG

Card Type: All · FPGA Type: CB · Function: 1 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:2	RO	All 0s	Reserved
P2_RST	1	RW	0	QSFP UserPort 2 Reset
P1_RST	0	RW	0	QSFP UserPort 1 Reset 1: Assert reset 0: De-assert reset

USRPRT_STAT_0_REG

Card Type: All · FPGA Type: CB · Function: 1 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:2	RO	All 0s	Reserved
P2_INT	1	RO	0	QSFP UserPort 2 Interrupt 1: Asserted 0: De-asserted
P1_INT	0	RO	0	QSFP UserPort 1 Interrupt 1: Asserted 0: De-asserted

USRPRT_CTRL_1_REG

Card Type: All · FPGA Type: CB · Function: 1 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:2	RO	All 0s	Reserved
P2_LP_MODE	1	RW	0	QSFP UserPort 2 LP Mode
P1_LP_MODE	0	RW	0	QSFP UserPort 1 LP Mode 1: Assert 0: De-assert

USRPRT_STAT_1_REG

Card Type: All · FPGA Type: CB · Function: 1 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:2	RO	All 0s	Reserved
P2_ PRSNT	1	RO	0	QSFP UserPort 2 Present 1: Asserted 0: De-asserted
P1_PRSNT	0	RO	0	QSFP UserPort 1 Present 1: Asserted 0: De-asserted

PHY_CTRL_REG

Card Type: All · FPGA Type: CB · Function: 1 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:4	RO	All 0s	Reserved
PHY_RST	3:0	RW	0x0	PHY 84991 Reset 0xD: Asserted Any other value: de-asserted. This Field is automatically cleared by FPGA after reset is issued.

Function 2

FPGA_REV_ID_REG

FUNC_CAP_0_REG

SCRTCH_n_REG

DEV_MSI_0_PEND_REG (TBD)

Card Type: All · FPGA Type: CB · Function: 2 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:1	RO	All 0s	Reserved
MBOX_INT	0	RO	0	1: MBOX requires service. 0: no service is requested.

DEV_MSI_0_INT_EN_REG (TBD)

Card Type: All · FPGA Type: CB · Function: 2 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:1	RO	0	Reserved
MBOX_INT_EN	0	RW	0	1: MBOX interrupt is enabled. 0: MBOX interrupt is disabled.

SPI_CMD_STAT_REG

SPI_ADD_REG

SPI_WR_DATA_REG

SPI_RD_DATA_REG

SPI_RST_REG

GEN_SPI_RD_DATA_REG

Card Type: All · FPGA Type: CB · Function: 2 · POR Value: 0x0000_0000

Data read from SPI Peripheral

Field	Bits	Type	Reset	Description
RD_DATA	31:0	RO	0	Data read back from SPI transaction. Number of bits based on #SPI_DATA_WIDTH The read back data is obtain each time write operation is carried out by writing into the GEN_SPI_WR_DATA_REG.

GEN_SPI_WR_DATA_REG

Card Type: All · FPGA Type: CB · Function: 2 · POR Value: 0x0000_0000

Data to be written into SPI Peripheral.

Field	Bits	Type	Reset	Description
WR_DATA	31:0	RW	0	Data to be written. Number of bits written based on #SPI_DATA_WIDTH Writing into this register will initiate the Generic SPI Master to send out the SPI transaction to the SPI Slave.

GEN_SPI_STAT

Card Type: All · FPGA Type: CB · Function: 2 · POR Value: 0x0000_0060

Status register for Generic SPI Master for SPI interface

Field	Bits	Type	Reset	Description
RSVD	30:9	RO	All 0s	Reserved
ERR_BIT	8	RO	0	Indicate overrun error has occur. 1: Transmit overrun error or receive overrun error has occur. 0: No overrun error has occurred. Recommendation: SW should check this bit before initiating a new command.
RRDY	7	RO	0	Indicate receive ready status. 1: SPI_RD_DATA_REG register contains valid data and is ready to be read. 0: SPI_RD_DATA_REG register does not contain valid data. Reading the SPI_RD_DATA_REG clears this register to 0.
TRRDY	6	RO	1	Indicate transmit ready status. 1: Transmit shift register is empty. 0: Transmit shift register is not empty. The SPI_WR_DATA_REG register is able to transmit data into transmit shift register only when this register field is set to empty.
TMT	5	RO	1	Indicate transmit shift register is empty. 1: Transmit shift register is empty. 0: Transmit shift register is not empty. When the transmit shift register is empty, the next data will be transferred from SPI_WR_DATA_REG register.
TOE	4	RO	0	Indicate transmit overrun error. 1: SPI_WR_DATA_REG register received new data before previous data was removed into the shift register.
ROE	3	RO	0	Indicate receive overrun error. 1: SPI_RD_DATA_REG register received new data before previous data was read. 0: No new data received before previous data was read.
RSVD	2:0	RO	0	Reserved

GEN_SPI_CTRL_REG

Card Type: All · FPGA Type: CB · Function: 2 · POR Value: 0x0000_0000

Instruct FPGA to select SPI peripheral and enable interrupt request.

Field	Bits	Type	Reset	Description
RSVD	31:11	RO	All 0s	Reserved.
SSO	10	RW	0	Control the Chip Select output pin based on the mask provided in SPI_SLV_SEL_REG register. 1: Assert the Chip Select for the SPI slave device 0: De-assert the Chip Select for the SPI slave device. SPI Master will continue to exchange data frames with correspondent SPI slave when this register field is asserted.
RSVD	9:8	RO	0	Reserved
IRRDY	7	RW	0	Enable interrupt request for receiver ready. 1: Interrupt enabled. 0: Interrupt disabled.
RSVD	6:0	RO	0	Reserved

GEN_SPI_CFG_CTRL_REG

Card Type: All · FPGA Type: CB · Function: 2 · POR Value: 0x0000_0210

Instruct FPGA to configure the SPI Master

Field	Bits	Type	Reset	Description
RSVD	31:15	RO	All 0s	Reserved.
SPI_MODE	14:13	RW	00	Control the SPI mode for the SPI transaction. 00 : Data sampled on rising edge and shifted out on falling edge (Clock polarity and clock phase is low.) 01 : Data sampled on the falling edge and shifted out on rising edge.(Clock polarity is low and clock phase is high) 10 : Data sampled on falling edge and shifted out on rising edge (Clock polarity is high and clock phase is low.) 11 : :Data sampled on rising edge and shifted out on falling edge (Clock polarity is high and clock phase is high.)
SPI_SHIFT_BIT	12	RW	0	Control whether the MSB or LSB bit is shifted out first. 0: MSB bit is shifted out first 1: LSB bit is shifted out first
SPI_CHP_SEL_DELAY	11:8	RW	0x2	Specify the delay based on half of the SPI clock period for the delay to send out the first data after Chip Select pin is asserted. 0x0: 0 SPI clock cycle 0x1: 0.5 SPI clock cycle 0x2: 1 SPI clock cycle …. 0xF: 7.5 SPI clock cycles
RSVD	7	RO	0	Reserved.
SPI_CLK_CNT	6:4	RW	001	The value in this field is the frequency divider of the system clock (75 MHz) to generate the serial clock for the SPI transaction. 000 75Mhz/2 (37.50 MHz) 001 75Mhz/4 (18.75 MHz) 010 75Mhz/6 (12.5 MHz) 011 75Mhz/8 (9.375 MHz) 100 75Mhz/10 (7.5 MHz) 101 75Mhz/12 (6.25 MHz) 110 75Mhz/14 (5.357 MHz) 111 75Mhz/16 (4.686 MHz) SPI clock frequency in MHz = 75MHz / (2 * (#SPI_CLK_CNT + 1)
RSVD	3:2	RO		Reserved.
SPI_DATA_WIDTH	1:0	RW	00	Specify number of bits send per each write or read transaction to the SPI slave. 00: 8 bits 01: 16 bits 10: 24 bits 11: 32 bits

GEN_SPI_SLV_SEL_REG

Card Type: All · FPGA Type: CB · Function: 2 · POR Value: 0x0000_0000

Instruct SPI Master to select which SPI slave to send transaction.

Field	Bits	Type	Reset	Description
SPI_SLV_SEL	31: 0	RW	All 0s	Bit 0: Control the SPI slave 0 enable for SPI master access where 1 is enable and 0 is disable. … Bit 31: Control the SPI slave 0 enable for SPI master access where 1 is enable and 0 is disable.

MDIO_STAT_CMD_REG

Card Type: All · FPGA Type: CB · Function: 2 · POR Value: 0x8000_0000

CPU Control of MDIO Master IP

Field	Bits	Type	Reset	Description
MDIO_STATUS	31	RO	1	0: MDIO transaction in progress 1: MDIO transaction completed It returns the status of the MDIO state machine. Once a CPU write to the MDIO register has taken place, the state machine begins to serialize the command to the transceiver. During this period, the status bit returns 0 every time the CPU reads from the register, and CPU writes will have no effect. As soon as the operation completes and the MDIO state machine has returned to idle, the status bit returns a one, and the CPU can safely read the data field or write a new command to the MDIO. This value is only cleared (1'b0) when a CPU MDIO transaction is pending or in progress. Otherwise it is set (1’b1) to represent that the last CPU MDIO transaction completed correctly.
RSVD	30	RO	0	Reserved
START	29:28	RW	0	Indicate the start of an MDIO transaction. These start bits differ between Clause 22 and Clause 45 MDIO. Note: Start bits are transmitted lsb first, so software must program them in reverse order as shown below. Clause 22 - start sequence 01, program start <= 10 Clause 45 - start sequence 00, program start <= 00
OPCODE	27:26	RW	All 0s	Determines the operation to be performed by the Management interface. The available opcodes differ between Clause 22 and Clause 45 MDIO. Clause 22 MDIO applies to 10/100/1000 Mbs MACs and Clause 45 MDIO applies to 10 GIG MACs. Note: Op-code bits are transmitted lsb first, so software must program them in reverse order as shown below. See long description for details. Clause 22 IEEE-opcode ASIC.opcode Description 00 00 - Not valid 01 10 - Write 10 01 - Read 11 11 - Not valid Clause 45 IEEE-opcode ASIC.opcode Description 00 00 Address 01 10 Write 11 11 Read 10 01 Post-read Increment Address
PHYAD	25:21	RW	All 0s	It indicates which of 32 possible physical devices transceivers attached to this bus is being addressed.
REGAD	20:16	RW	All 0s	It indicates which of 32 possible registers within the physical device the CPU wishes to read/write.
DATA	15:0	RW	All 0s	The value in this field corresponds to the 16 bit value defined in the physical layer device data sheet or the 802.3u specification. On writes to the physical layer device, management would write the value to be sent to the physical layer device in this field while it was writing the opcode and address fields. On reads from the physical layer device, management will write the opcode and address fields. It will then monitor the status bit. When status bit is set (idle), it knows the data field has the value read from the physical layer device. Writes to this field are ignored when not idle. Reads of this field may contain invalid data when not idle.

MDIO_CTRL_REG

Card Type: All · FPGA Type: CB · Function: 2 · POR Value: 0x00F8_0007

General control of MDIO Master IP

Field	Bits	Type	Reset	Description
RSVD	31:24	RO	All 0s	Reserved
MDIO_PREAMBLE_CNT	23:19	RW	1F	Programmable preamble for both CPU and MDIO Stack issued MDIO commands. NOTE: For proper operation with some Phys, this value should be set to 31.
RSVD	18:12	RO	All 0s	Reserved
STACK_EN	11	RW	0	1: Enables the MDIO Stack. 0: Disable MDIO Stack. MDIO under CPU control with MDIO_STAT_CMD_REG.
RSVD	10:8	RO	All 0s	Reserved
MDIO_PROG_CLK_DIV	7:0	RW	7	This register sets the mdio clock divide rate. Period of clock = ((MDIO_PROG_CLK_DIV + 1)13.33ns)2 14 (8’hE) : 2.5 MHz 7 (8’h7) : 4.6875 MHZ 4 (8’h4) : 7.5 MHz 2 (8’h2) : 12.5 MHz 0 (8’h0) : 37.5 MHz

MDIO_STK_CTRL_REG

Card Type: All · FPGA Type: CB · Function: 2 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:1	RO	0	Reserved
STACK_CMD_START	0	RW	0	1: Enables MDIO stack operation 0: Legacy CPU-only operation using MDIO_STAT_CMD_REG. Note: Stack will stop executing after the current instruction if #STACK_EN is disabled before #STACK_END_ADD MDIO instruction is reached. #STACK_END_ADD is the address of #STACK_START_ADD + #STACK_NUM_CMDS

MDIO_STK_ADDR_CONF_REG

Card Type: All · FPGA Type: CB · Function: 2 · POR Value: 0x0000_0080

Field	Bits	Type	Reset	Description
RSVD	31:19	RO	0	Reserved
STACK_PROG_DELAY	18:14	RW	All 0s	The number of MDIO clock cycles (MDC) to way in between each MDIO stack command. (This is provided just in case some PHY has issues with quick back-to-back MDIO transactions.)
STACK_NUM_CMDS	13:7	RW	1	The number of MDIO Stack RAM instructions/entries to execute starting at #STACK_START_ADDR. (Notes: Reading past the end of the stack is also and END condition)
STACK_START_ADDR	6:0	RW	All 0s	Starting MDIO instruction in the stack to begin executing when #STACK_CMD_START and #STACK_EN are set

MDIO_STK_STAT_REG

Card Type: All · FPGA Type: CB · Function: 2 · POR Value: 0x0000_0003

Field	Bits	Type	Reset	Description
RSVD	31:2	RO	0	Reserved
STACK_IDLE	1	RO	1	For DEBUG use only, should not use by SW Indicates that the MDIO stack has completed its instruction and there are no longer any MDIO commands to be executed. This field will be cleared whenever a new MDIO stack instruction has been issued with a non-zero number of MDIO commands.
STACK_CMD_DONE	0	RO	1	1: Stack processing done for all MDIO transactions of a given MDIO stack instruction specified in MDIO_STK_ADDR_CONF_REG and started from MDIO_STK_CTRL_REG. It also means the last #STACK_NUM_CMDS number of commands it was instructed to execute have been successfully completed. 0: This value is only cleared when the MDIO Stack has MDIO transactions pending or in progress

MDIO_STK_RAM_DATA_REG

Card Type: All · FPGA Type: CB · Function: 2 · POR Value: 0x0000_0000

Individual stack value entry for corresponding #STACK_ADDR

Field	Bits	Type	Reset	Description
RSVD	31:30	RO	All 0s	Reserved
START	29:28	RW	All 0s	See MDIO_STAT_CMD_REG #START
OPCODE	27:26	RW	All 0s	See MDIO_STAT_CMD_REG #OPCODE
PHYAD	25:21	RW	All 0s	See MDIO_STAT_CMD_REG #PHYAD
REGAD	20:16	RW	All 0s	See MDIO_STAT_CMD_REG #REGAD
DATA	15:0	RW	All 0s	See MDIO_STAT_CMD_REG #DATA

MDIO_STK_RAM_ADDR_REG

Card Type: All · FPGA Type: CB · Function: 2 · POR Value: 0x0000_0000

MDIO Stack address

Field	Bits	Type	Reset	Description
RSVD	31:8	RO	0	Reserved
STACK_ADDR	7:0	RW	0	Indicates address/position of stack that MDIO_STK_RAM_DATA_REG is writing/reading to

MDIO_STAT_INT_REG

Card Type: All · FPGA Type: CB · Function: 2 · POR Value: 0x0000_0000

MDIO Status interrupt

Field	Bits	Type	Description
RSVD	31:6	RO	Reserved
MDIO_STATUS_INT	5	W1C	Indicates a Single MDIO transaction is completed
STK_CMD_DONE_INT	4	W1C	Indicates a new stack of MDIO transactions is done.
RSVD	3:2	RO	Reserved
MDIO_STATUS_INT_EN	1	RW	Enable Single MDIO interrupt (rising edge of MDIO_STAT_CMD_REG #MDIO_STATUS)
STK_CMD_DONE_INT_EN	0	RW	Enable Stack MDIO interrupt (rising edge of MDIO_STK_STAT_REG #STK_CMD_DONE)

Function 3

FPGA_REV_ID_REG

FUNC_CAP_0_REG

SCRTCH_n_REG

DEV_MSI_0_PEND_REG (TBD)

Card Type: All · FPGA Type: CB · Function: 3 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:1	RO	All 0s	Reserved
MBOX_INT	0	RO	0	1: MBOX requires service. 0: no service is requested.

DEV_MSI_0_INT_EN_REG (TBD)

Card Type: All · FPGA Type: CB · Function: 3 · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:1	RO	0	Reserved
MBOX_INT_EN	0	RW	0	1: MBOX interrupt is enabled. 0: MBOX interrupt is disabled.

I2C_PRSCL_LO_REG

I2C_PRSCL_HI_REG

I2C_CTRL_REG

I2C_TX_REG

I2C_RX_REG

I2C_CMD_REG

I2C_STAT_REG

I2C_MUX_SEL_REG

I2C_RST_REG

SWB Registers

FPGA_REV_ID_REG

FPGA_RECONFIG_CTRL_REG

FPGA_RECONFIG_STAT_REG

SCRTCH_n_REG

SWB_INFO_REG

Card Type: All · FPGA Type: SWB · Function: none · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:1	RO	All 0s	Reserved
TRAY_2_ID	11:8	RO	All 0s	Current Tray 2 ID value
TRAY_1_ID	7:4	RO	All 0s	Current Tray 1 ID value
RSVD	3:1	RO	All 0s	Reserved
SWB_ID	0	RO	0	Current SWB ID 0: SWB0 1: SWB1

PWR_STAT_REG

Card Type: All · FPGA Type: SWB · Function: none · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:1	RO	All 0s	Reserved
SWB_ALL_PGOK	16	RO	0	Indicates SWB power sequencing is completed 1: Asserted 0: De-asserted
RSVD	15:1	RO	All 0s	Reserved
TH6_VDD_CORE_VRM_INT	0	RO	0	TH6 VDD Power Interrupt 1: Asserted 0: De-asserted

CB_CTRL_REG

Card Type: All · FPGA Type: SWB · Function: None · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:12	RO	All 0s	Reserved
LSB_RST_SWB	11:8	RW	0	Reset control of remote LSB 0xD: Asserted Any other value: de-asserted. When asserted by SW, will reset the SWB LSB port and all related processors. This Field is automatically cleared by FPGA after reset is issued.
RSVD	7:0	RO	0	Reserved

CB_STAT_REG

Card Type: All · FPGA Type: SWB · Function: none · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:28	RO	All 0s	Reserved
LSB_PROC_TYP_ERR	27	RO	0	One of the processors in LSB port received a packet with an invalid value in type field.
LSB_PROC_FATAL_ERR	26	RO	0	One of the state machines in one of the processors in LSB port has gone momentarily to unknown state.
LSB_PROC_EOP_ERR	25	RO	0	One of the processors in LSB port received a packet without EOP.
LSB_PROC_SOP_ERR	24	RO	0	One of the processors in LSB port received a packet without SOP.
RSVD	23:19	RO	0	Reserved
LSB_TX_FATAL_ERR	18	RO	0	One of the state machines in LSB TX PHY has gone momentarily to unknown state.
LSB_TX_EOP_ERR	17	RO	0	LSB TX PHY received a packet without EOP from one of the processors.
LSB_TX_SOP_ERR	16	RO	0	LSB TX PHY received a packet without SOP from one of the processors.
RSVD	15	RO	0	Reserved
LSB_RX_REV_NO_ERR	14	RO	0	REV of the received packet does not match with the REV_NO of the LSB RX PHY.
LSB_RX_UNEXP_ERR	13	RO	0	Unexpected condition in LSB RX PHY. 1: means RX_BUF is almost full or LSB_RX_PHY_CTRL has received a packet without SOP from DES (deserializer)
LSB_RX_SEQNO_ERR	12	RO	0	LSB RX PHY received a packet from remote party with invalid SEQ no.
LSB_RX_DEV_ID_ERR	11	RO	0	LSB RX PHY received a packet from remote party with invalid DEV-ID.
LSB_RX_FATAL_ERR	10	RO	0	One of the state machines in LSB RX PHY has gone momentarily to unknown state.
LSB_RX_LNGTH_ERR	9	RO	0	LSB RX PHY received a packet from remote party with invalid Length.
LSB_RX_CHKSM_ERR	8	RO	0	LSB RX PHY received a packet from remote party with checksum error.
RSVD	7:0	RO	0	Reserved

ASIC_CTRL_REG

Card Type: All · FPGA Type: SWB · Function: none · POR Value: 0x00DD_03DD

Field	Bits	Type	Reset	Description
RSVD	31:24	RO	All 0s	Reserved
M0_CORE_RST	23:20	RW	0xD	M0 Core Reset 0: Asserted 1: De-asserted
R8_CORE_RST	19:16	RW	0xD	R8 Core Reset 0: Asserted 1: De-asserted
RSVD	15:14	RO	All 0s	Reserved
TH6_PCIE_LANE	13:12	RW	0x0	Select the maximum link width of PCIe interface: 0: x1 / x2 / x4 link width 1: x1 link width 2: x1 or x2 link width 3: Reserved
RSVD	11:10	RO	All 0s	Reserved
TH6_PCIE_GEN	9:8	RW	0x3	Select the operating rate of PCIe interface: 0: Gen1 1: Gen2 2: Gen3 3: Gen4
TH6_PERST	7:4	RW	0xD	TH6 PCIe Reset 0xD: Asserted Any other value: de-asserted. This Field is NOT automatically cleared by FPGA after reset is issued.
TH6_SYS_RST	3:0	RW	0xD	TH6 System Reset 0xD: Asserted Any other value: de-asserted. This Field is NOT automatically cleared by FPGA after reset is issued.

ASIC_STAT_REG

Card Type: All · FPGA Type: SWB · Function: none · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:1	RO	All 0s	Reserved
TH6_PHY_LINK_UP	0	RO	0	TH6 PHY Link status 1: Link is up 0: Link is down

RTM_CTRL_REG

Card Type: All · FPGA Type: SWB · Function: none · POR Value: 0x0000_011D

Field	Bits	Type	Reset	Description
RSVD	31:9	RO	All 0s	Reserved
RTM_MODESEL	8	RW	1	Enable of Mode Select of all Retimer (1-56) 1: Shared SPI ROM 0: Single SPI ROM
RSVD	7:5	RO	All 0s	Reserved
RTM_SERBOOT	4	RW	1	Enable of Serial Boot of all Retimers (1-56) 1: from SPI ROM 0: from MDIO
RTM_RST	3:0	RW	0xD	Reset of all Retimers (1-56) 0xD: Asserted Any other value: de-asserted. This Field is NOT automatically cleared by FPGA after reset is issued.

THRM_STAT_REG

Card Type: All · FPGA Type: SWB · Function: None · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:2	RO	All 0s	Reserved
TH6_TS_HW_OTP_INT	1	RO	0	TH6 thermal diodes temperature sensor HW OTP shutdown interrupt 1: Asserted 0: De-asserted
EXT_TEMPSNSR_ALERT	0	RO	0	Multiple external temperature sensor alert 1: Asserted 0: De-asserted

EN_ACCSS_PRTCTD_REG

This register is to protect critical registers from accidental writes. SW should write 0x8F35_D72C in order to have write access to protected registers.

Card Type: All · FPGA Type: PMC · Function: None · POR Value: 0x0000_0000

Enables access to protected registers.

Field	Bits	Type	Reset	Description
EN_ACCSS	31:0	RW	0	0x8F35_D72C: Enables access to protected registers. Other Values: Disables access to protected registers.

I2C_MUX_RST_REG

Card Type: All · FPGA Type: SWB · Function: none · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:8	RO	All 0s	Reserved
I2C_MUX1_RST	7:4	RW	0x0	Reset control of I2C MUX which has I2Cs of CB_FPGA to SWB external temperature sensors. 0xD: Asserted Any other value: de-asserted. This Field is NOT automatically cleared by FPGA after reset is issued.
I2C_MUX0_RST	3:0	RW	0x0	Reset control of I2C MUX which has I2Cs of CB_FPGA to clock gen, EEPROM and tray cartridge 0xD: Asserted Any other value: de-asserted. This Field is NOT automatically cleared by FPGA after reset is issued.

SPI_MUX_REG

Card Type: All · FPGA Type: SWB · Function: none · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:9	RO	All 0s	Reserved
TH6_SPI_MUX_SEL	8	RW	0	MUX Select for TH6 SPI flash connection from: 1: SWB FPGA 0: TH6 ASIC
RSVD	7:4	RO	All 0s	Reserved
SWB_SPI_MUX_SEL	4	RW	0	MUX Select for SWB SPI flash connection from: 1: CB FPGA 0: SWB FPGA
RSVD	3:1	RO	All 0s	Reserved
CB_SPI_MUX_SEL	0	RW	0	MUX Select for CB SPI connection to: 1: Direct access to SWB SPI Flash 0: Pass-through SWB_FPGA (to access TH6 SPI flash)

FLSH_CTRL_REG

This register is clear under two conditions only.

Upon assertion of global reset.
Power cycle Card Type: All · FPGA Type: SWB · Function: None · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:13	RO	All 0s	Reserved
RTM_FLSH_WP	12	RW	0	Retimers Flash Write Protect 1: Protected, Once asserted, FPGA will not issue any write/erase command to the flash. Once asserted, cannot be de-asserted by SW.
RSVD	11:9	RO	All 0s	Reserved
TH6_FLSH_WP	8	RW	0	TH6 Flash Write Protect 1: Protected, Once asserted, FPGA will not issue any write/erase command to the flash. Once asserted, cannot be de-asserted by SW.
RSVD	7:5	RO	All 0s	Reserved
DIAG_EEPRM_WP	4	RW	0	Diagnostic EEPROM Write Protect 1: Protected, Once asserted, FPGA will not issue any write/erase command to the flash. Once asserted, cannot be de-asserted by SW.
RSVD	3:2	RO	All 0s	Reserved
FPGA_FLSH_WP	1	RW	0	FPGA (CB) Flash Write Protect 1: Protected, Once asserted, FPGA will not issue any write/erase command to the flash. Once asserted, cannot be de-asserted by SW.
RSVD	0	RO	0	Reserved

TND_PWR_CTRL_0_REG

This is a protected register by EN_ACCSS_PRTCTD_REG.

Card Type: All · FPGA Type: SWB · Function: none · POR Value: 0x001F_FFFF

Field	Bits	Type	Reset	Description
RSVD	31:30	RO	All 0s	Reserved
DIPSW_DEBUGBOOT	29	RW	0	Debug Boot value
JMP_3ASTG_BOOT	28	RW	0	3AStg Boot value
RSVD	27:25	RO	All 0s	Reserved
PSSM_OVR	24	RW	0	Enable override of PSSM 1: Enable 0: Disable
RSVD	23:21	RO	All 0s	Reserved
PWREN_PVDD1V2_1	20	RW	1
PWREN_PVDD1V2_0	19	RW	1
PWREN_PVDD1V8_DUT	18	RW	1
PWREN_PVDD_MDIO	17	RW	1
PWREN_P1V8_DVDDIO_4	16	RW	1
PWREN_P1V8_DVDDIO_3	15	RW	1
PWREN_P1V8_DVDDIO_2	14	RW	1
PWREN_P1V8_DVDDIO_1	13	RW	1
PWREN_P0V75_DVDD_57	12	RW	1
PWREN_P0V75_DVDD_50	11	RW	1
PWREN_P0V75_DVDD_43	10	RW	1
PWREN_P0V75_DVDD_36	9	RW	1
PWREN_P0V75_DVDD_21	8	RW	1
PWREN_P0V75_DVDD_14	7	RW	1
PWREN_P0V75_DVDD_7	6	RW	1
PWREN_P0V75_DVDD_0	5	RW	1
PWREN_P1V8	4
PWREN_PVDD_3V_SYNTH_LDO_B1	3	RW	1
PWREN_PVDD_3V_SYNTH_LDO_A1	2	RW	1
PWREN_P3V3	1	RW	1
PWREN_P5V_STBY	0	RW	1

TND_PWR_CTRL_1_REG

This is a protected register by EN_ACCSS_PRTCTD_REG.

Card Type: All · FPGA Type: SWB · Function: none · POR Value: 0x3FFF_FFFF

Field	Bits	Type	Reset	Description
RSVD	31:30	RO	All 0s	Reserved
CLKEN_BOT_TOP_PLL_CLKIN	29	RW	1
PWREN_PVDD1V2_T3	28	RW	1
PWREN_PVDD1V45_3	27	RW	1
PWREN_PVDD1V45_2	26	RW	1
PWREN_PVDD1V45_1	25	RW	1
PWREN_PVDD1V45_0	24	RW	1
PWREN_P1V5_CNDR1	23	RW	1
PWREN_P1V5_CNDR0	22	RW	1
PWREN_PVDD1V5_ANLG	21	RW	1
PWREN_PVDD_0V9_3	20	RW	1
PWREN_PVDD_0V9_2	19	RW	1
PWREN_PVDD_0V9_1	18	RW	1
PWREN_PVDD_0V9_0	17	RW	1
PWREN_PVDD_0V9_ANLG_1	16	RW	1
PWREN_PVDD_0V9_ANLG_0	15	RW	1
PWREN_PVDD0_8V_T3	14	RW	1
PWREN_PVDDA_PHYT3_P3	13	RW	1
PWREN_PVDDA_PHYT2_P2	12	RW	1
PWREN_PVDDA_PHYT1_P1	11	RW	1
PWREN_PVDD0V75_ANLG_1	10	RW	1
PWREN_PVDD0V75_ANLG_0	9	RW	1
PWREN_PVDD_PHYTILE_7	8	RW	1
PWREN_PVDD_PHYTILE_6	7	RW	1
PWREN_PVDD_PHYTILE_5	6	RW	1
PWREN_PVDD_PHYTILE_4	5	RW	1
PWREN_PVDD_PHYTILE_3	4	RW	1
PWREN_PVDD_PHYTILE_2	3	RW	1
PWREN_PVDD_PHYTILE_1	2	RW	1
PWREN_PVDD_PHYTILE_0	1	RW	1
PWREN_FM_PVDD_CORE	0	RW	1

TND_PWR_STAT_0_REG

Card Type: All · FPGA Type: SWB · Function: none · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
PG_P0V75_DVDD_26	31
PG_P0V75_DVDD_25	30
PG_P0V75_DVDD_24	29
PG_P0V75_DVDD_23	28
PG_P0V75_DVDD_22	27
PG_P0V75_DVDD_21	26
PG_P0V75_DVDD_20	25
PG_P0V75_DVDD_19	24
PG_P0V75_DVDD_18	23
PG_P0V75_DVDD_17	22
PG_P0V75_DVDD_16	21
PG_P0V75_DVDD_15	20
PG_P0V75_DVDD_14	19
PG_P0V75_DVDD_13	18
PG_P0V75_DVDD_12	17
PG_P0V75_DVDD_11	16
PG_P0V75_DVDD_10	15
PG_P0V75_DVDD_9	14
PG_P0V75_DVDD_8	13
PG_P0V75_DVDD_7	12
PG_P0V75_DVDD_6	11
PG_P0V75_DVDD_5	10
PG_P0V75_DVDD_4	9
PG_P0V75_DVDD_3	8
PG_P0V75_DVDD_2	7
PG_P0V75_DVDD_1	6
PG_P0V75_DVDD_0	5
PG_P1V8	4
PG_PVDD_3V_SYNTH_LDO_B1	3
PG_PVDD_3V_SYNTH_LDO_A1	2
PG_P3V3	1
PG_P5V_STBY	0

TND_PWR_STAT_1_REG

Card Type: All · FPGA Type: SWB · Function: none · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
PG_P1V8_DVDDIO_3	31
PG_P1V8_DVDDIO_2	30
PG_P1V8_DVDDIO_1	29
PG_P0V75_DVDD_63	28
PG_P0V75_DVDD_62	27
PG_P0V75_DVDD_61	26
PG_P0V75_DVDD_60	25
PG_P0V75_DVDD_59	24
PG_P0V75_DVDD_58	23
PG_P0V75_DVDD_57	22
PG_P0V75_DVDD_56	21
PG_P0V75_DVDD_55	20
PG_P0V75_DVDD_54	19
PG_P0V75_DVDD_53	18
PG_P0V75_DVDD_52	17
PG_P0V75_DVDD_51	16
PG_P0V75_DVDD_50	15
PG_P0V75_DVDD_49	14
PG_P0V75_DVDD_48	13
PG_P0V75_DVDD_47	12
PG_P0V75_DVDD_46	11
PG_P0V75_DVDD_45	10
PG_P0V75_DVDD_44	9
PG_P0V75_DVDD_43	8
PG_P0V75_DVDD_42	7
PG_P0V75_DVDD_41	6
PG_P0V75_DVDD_40	5
PG_P0V75_DVDD_39	4
PG_P0V75_DVDD_38	3
PG_P0V75_DVDD_37	2
PG_P0V75_DVDD_36	1
PG_P0V75_DVDD_27	0

TND_PWR_STAT_2_REG

Card Type: All · FPGA Type: SWB · Function: none · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
PG_PVDD1V45_2	31
PG_PVDD1V45_1	30
PG_PVDD1V45_0	29
PG_P1V5_CNDR1	28
PG_P1V5_CNDR0	27
PG_PVDD1V5_ANLG	26
PG_PVDD_0V9_3	25
PG_PVDD_0V9_2	24
PG_PVDD_0V9_1	23
PG_PVDD_0V9_0	22
PG_PVDD_0V9_ANLG_1	21
PG_PVDD_0V9_ANLG_0	20
PG_PVDD0_8V_T3	19
PG_PVDDA_PHYT3_P3	18
PG_PVDDA_PHYT2_P2	17
PG_PVDDA_PHYT1_P1	16
PG_PVDD0V75_ANLG_1	15
PG_PVDD0V75_ANLG_0	14
PG_PVDD_PHYTILE_7	13
PG_PVDD_PHYTILE_6	12
PG_PVDD_PHYTILE_5	11
PG_PVDD_PHYTILE_4	10
PG_PVDD_PHYTILE_3	9
PG_PVDD_PHYTILE_2	8
PG_PVDD_PHYTILE_1	7
PG_PVDD_PHYTILE_0	6
PG_FM_PVDD_CORE	5
PG_PVDD1V2_1	4
PG_PVDD1V2_0	3
PG_PVDD1V8_DUT	2
PG_PVDD_MDIO	1
PG_P1V8_DVDDIO_4	0

TND_PWR_STAT_3_REG

Card Type: All · FPGA Type: SWB · Function: none · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:2	RO	All 0s	Reserved
PG_PVDD1V2_T3	1
PG_PVDD1V45_3	0

TND_CB_GPIO_CTRL_REG

Card Type: All · FPGA Type: SWB · Function: None · POR Value: 0x0000_0000

Field	Bits	Type	Description
RSVD	31:8	RO	Reserved
GPI_7	7	RW
GPI_6	6	RW	1: Assert GPIO 6 0: De-assert GPIO 6
RSVD	5:0	RO	Reserved

TND_CB_GPIO_STAT_REG

Card Type: All · FPGA Type: SWB · Function: None · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:8	RO	All 0s	Reserved
GPO_7	7	RO	0
GPO_6	6	RO	0	1: GPIO 6 is asserted 0: GPIO 6 is de-asserted
RSVD	5:0	RO	All 0s	Reserved

TND_CB_GPIO_DIR_CTRL_REG

Card Type: All · FPGA Type: SWB · Function: None · POR Value: 0x0000_0000

Field	Bits	Type	Description
RSVD	31:8	RO	Reserved
GPIO_DIR_7	7	RW
GPIO_DIR_6	6	RW	1: Indicate GPIO 6 is configured as output and register GPIO_CTRL_REG is used to control this output port value. 0: Indicate GPIO 6 is configured as input and register GPIO_STAT_REG store this input port value.
RSVD	5:0	RO	Reserved

RST_CAUSE_REG

This is a protected register. This is sticky and does not get reset under global reset condition.

Card Type: All · FPGA Type: SWB · Function: None · POR Value: 0x0000_0001

Field	Bits	Type	Reset	Description
SW_RST_COOKIES	31:16	RW	All 0s	For SW to read and write.
RSVD	11:9	RO	All 0s	Reserved.
CLD_RST	8	W1C	0	This bit will be set if the System PGOOD is de-sserted from a good state.
RSVD	7:1	RO	All 0s	Reserved.
PWR_ON_RST	0	W1C	1

ICB Registers

FPGA_REV_ID_REG

FPGA_RECONFIG_CTRL_REG

FPGA_RECONFIG_STAT_REG

SCRTCH_n_REG

PWR_CTRL_REG

Card Type: All · FPGA Type: ICB · Function: none · POR Value: 0x0000_0099

Field	Bits	Type	Reset	Description
PWR_SUICIDE	31:16	RW	All 0s	Value of 0xA73D in this register will disable 1Khz signal sent out to the hardware external watchdog and toggle the reconfiguration pin of ICB. This field is used for ICB post-ISP update.
RSVD	15:8	RO	All 0s	Reserved.
P12V_VRM_EN_SWB_1	7:4	RW	0x9	SWB1 VRM enable 0x6: Enable 0x9: Disable Although any value can be written in this field by SW, but FPGA will not take action if the value is not 0x6 or 0x9 and will keep the previous Enable/Disable status.
P12V_VRM_EN_SWB_0	3:0	RW	0x9	SWB0 VRM enable 0x6: Enable 0x9: Disable Although any value can be written in this field by SW, but FPGA will not take action if the value is not 0x6 or 0x9 and will keep the previous Enable/Disable status.

PWR_STAT_REG

Card Type: All · FPGA Type: ICB · Function: none · POR Value: 0x0000_00F7

Field	Bits	Type	Reset	Description
RSVD	31:21	RO	All 0s	Reserved
ALRT_P50V_FAN_8	20	RO	0
ALRT_P50V_FAN_7	19	RO	0
ALRT_P50V_FAN_6	18	RO	0
ALRT_P50V_FAN_5	17	RO	0
ALRT_P50V_FAN_4	16	RO	0	Alert from Fan 4 1: Asserted 0: De-asserted
RSVD	15:13	RO	All 0s	Reserved
PG_P50V_FAN_8	12	RO	0
PG_P50V_FAN_7	11	RO	0
PG_P50V_FAN_6	10	RO	0
PG_P50V_FAN_5	9	RO	0
PG_P50V_FAN_4	8	RO	0	Power status of Fan 4 1: Power is ok
ALRT_P50V_HSC_STBY	7	RO	1	Alert from hotswap controller standby 1: Asserted 0: De-asserted
ALRT_P50V_HSC_MAIN	6	RO	1	Alert from hotswap controller main 1: Asserted 0: De-asserted
PRSNT_P50V_HSC_STBY	5	RO	1	Present status of hotswap controller standby 1: Present 0: Not present
PRSNT_P50V_HSC_MAIN	4	RO	1	Present status hotswap controller main 1: Present 0: Not present
RSVD	3	RO	0	Reserved
PG_P50V_HSC_STBY	2	RO	1	Power status of hotswap controller standby 1: Power is ok
PG_P50V_HSC_MAIN	1	RO	1	Power status of hotswap controller main 1: Power is ok
PG_P3V3_STBY	0	RO	1	Power status of P3V3 Standby power rail 1: Power is ok

FAN_CTRL_REG

Card Type: All · FPGA Type: ICB · Function: none · POR Value: 0x0006_6666

Field	Bits	Type	Reset	Description
RSVD	31:20	RO	All 0s	Reserved.
P50V_EFUSE_EN_FAN_8	19:16	RW	0x6	Fan 8 EFUSE enable 0x6: Enable 0x9: Disable Although any value can be written in this field by SW, but FPGA will not take action if the value is not 0x6 or 0x9 and will keep the previous Enable/Disable status. (Exception: this signal will automatically clear when fan is not present)
P50V_EFUSE_EN_FAN_7	15:12	RW	0x6	Fan 7 EFUSE enable 0x6: Enable 0x9: Disable Although any value can be written in this field by SW, but FPGA will not take action if the value is not 0x6 or 0x9 and will keep the previous Enable/Disable status. (Exception: this signal will automatically clear when fan is not present)
P50V_EFUSE_EN_FAN_6	11:8	RW	0x6	Fan 6 EFUSE enable 0x6: Enable 0x9: Disable Although any value can be written in this field by SW, but FPGA will not take action if the value is not 0x6 or 0x9 and will keep the previous Enable/Disable status. (Exception: this signal will automatically clear when fan is not present)
P50V_EFUSE_EN_FAN_5	7:4	RW	0x6	Fan 5 EFUSE enable 0x6: Enable 0x9: Disable Although any value can be written in this field by SW, but FPGA will not take action if the value is not 0x6 or 0x9 and will keep the previous Enable/Disable status. (Exception: this signal will automatically clear when fan is not present)
P50V_EFUSE_EN_FAN_4	3:0	RW	0x6	Fan 4 EFUSE enable 0x6: Enable 0x9: Disable Although any value can be written in this field by SW, but FPGA will not take action if the value is not 0x6 or 0x9 and will keep the previous Enable/Disable status. (Exception: this signal will automatically clear when fan is not present)

FAN_STAT_REG

Card Type: All · FPGA Type: ICB · Function: none · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:13	RO	All 0s	Reserved
FAN_FULL_SPD	12	RO	0	Fan speed status 1: Fan is at full speed 0: Fan is not at full speed (buffered signal from CB FPGA)
RSVD	11:9	RO	All 0s	Reserved
FAN_CTRLR_INT	8	RO	0	Interrupt status of fan controller (fan 4-8) 1: Asserted 0: De-asserted
RSVD	7:5	RO	All 0s	Reserved
PRSNT_FAN_8	4	RO	0
PRSNT_FAN_7	3	RO	0
PRSNT_FAN_6	2	RO	0
PRSNT_FAN_5	1	RO	0
PRSNT_FAN_4	0	RO	0	Fan 4 presence status 1: Present 0: Not present

THRM_STAT_REG

Card Type: All · FPGA Type: ICB · Function: none · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:2	RO	All 0s	Reserved
TMP75_ALRT	1	RW	0	Interrupt from temperature sensor TMP75 1: Asserted 0: De-asserted
TMP432_ALRT	0	RW	0	Interrupt from temperature sensor TMP432 1: Asserted 0: De-asserted

EN_ACCSS_PRTCTD_REG

This register is to protect critical registers from accidental writes. SW should write 0x8F35_D72C in order to have write access to protected registers.

Card Type: All · FPGA Type: ICB · Function: none · POR Value: 0x0000_0000

Enables access to protected registers.

Field	Bits	Type	Reset	Description
EN_ACCSS	31:0	RW	0	0x8F35_D72C: Enables access to protected registers. Other Values: Disables access to protected registers.

I2C_MUX_RST_REG

Card Type: All · FPGA Type: ICB · Function: none · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:4	RO	All 0s	Reserved
I2C_MUX_RST	3:0	RW	0x0	Reset control of I2C MUX Channel 4 – VRM and Fan EFUSE. 0xD: Asserted Any other value: de-asserted. This Field is NOT automatically cleared by FPGA after reset is issued.

FLSH_CTRL_REG

This register is clear under two conditions only.

Upon assertion of global reset.
Power cycle Card Type: All · FPGA Type: ICB · Function: None · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:1	RO	All 0s	Reserved
FRU_EEPRM_WP	0	RW	0	FRU EEPROM Write Protect 1: Protected, Once asserted, cannot be de-asserted by SW.

LED_SYNC_REG

LED_CONFIG_REG

LED_CTRL_REG

For bit definitions please refer to the section “LED Control bits”.

Card Type: All · FPGA Type: ICB · Function: none · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:8	RO	All 0s	Reserved
FAN_ALRT_STAT	7:0	RW	0x0	Fan Alert LED status

TND_CB_GPIO_CTRL_REG

Card Type: All · FPGA Type: ICB · Function: None · POR Value: 0x0000_0000

Field	Bits	Type	Description
RSVD	31:4	RO	Reserved
GPI_3	3	RW
GPI_2	2	RW
GPI_1	1	RW	1: Assert GPIO 1 0: De-assert GPIO 1
RSVD	0	RO	Reserved

TND_CB_GPIO_STAT_REG

Card Type: All · FPGA Type: SWB · Function: None · POR Value: 0x0000_0000

Field	Bits	Type	Reset	Description
RSVD	31:4	RO	All 0s	Reserved
GPO_3	3	RO	0
GPO_2	2	RO	0
GPO_1	1	RO	0	1: GPIO 1 is asserted 0: GPIO 1 is de-asserted
RSVD	0	RO	0	Reserved

TND_CB_GPIO_DIR_CTRL_REG

Card Type: All · FPGA Type: ICB · Function: None · POR Value: 0x0000_0000

Field	Bits	Type	Description
RSVD	31:4	RO	Reserved
GPIO_DIR_3	3	RW
GPIO_DIR_2	2	RW
GPIO_DIR_1	1	RW	1: Indicate GPIO 1 is configured as output and register GPIO_CTRL_REG is used to control this output port value. 0: Indicate GPIO 1 is configured as input and register GPIO_STAT_REG store this input port value.
RSVD	0	RO	Reserved

178 KiB Raw Blame History Unescape Escape

Blanton (Project Helios) FPGA Register Specification

Contents

1. Revision History

2. Document Abbreviations

3. Register Address Map

CB — Control Board

CB — Function 0

CB — Function 1

CB — Function 2

CB — Function 3

SWB — Switch Board

SWB — Function none

ICB — PDB / Power Distribution Board

ICB — Function none

Common

none — Function none

4. MSI Interrupt Mapping

CB MSI Vector Map

SWB Interrupt Map

ICB Interrupt Map

5. Register Descriptions

MSI Interrupts

Interrupt registers

DEV_MSI_PEND_REG

DEV_MSI_INT_EN_REG

MSI Generation

LED Control bits

Common Register Description

FPGA_REV_ID_REG

RDND_MGMT_REG

FUNC_CAP_0_REG

FUNC_CAP_1_REG

FUNC_CAP_2_REG

FUNC_CAP_3_REG

FUNC_CAP_4_REG

FUNC_CAP_5_REG

FUNC_CAP_6_REG

FUNC_CAP_7_REG

FUNC_CAP_8_REG

MBOX_n_DATA_REG

MBOX_STAT_REG

MBOX_STAT_PLRTY_REG

MBOX_STAT_EDG_LVL_REG

MBOX_STAT_INT_EN_REG

MBOX_STAT_INT_STAT_REG

MBOX_STAT_INT_CLR_REG

SCRTCH_n_REG

SEM_REG

SPI_CMD_STAT_REG

SPI_ADD_REG

SPI_WR_DATA_REG

SPI_RD_DATA_REG

SPI_RST_REG

I2C_PRSCL_LO_REG

I2C_PRSCL_HI_REG

I2C_CTRL_REG

I2C_TX_REG

I2C_RX_REG

I2C_CMD_REG

I2C_STAT_REG

I2C_MUX_SEL_REG

I2C_RST_REG

LED_SYNC_REG

LED_CONFIG_REG

FPGA_RECONFIG_CTRL_REG

FPGA_RECONFIG_STAT_REG

CB Registers

Function 0

FPGA_REV_ID_REG

FUNC_CAP_0_REG

FPGA_RECONFIG_CTRL_REG

FPGA_RECONFIG_STAT_REG

SCRTCH_n_REG

DEV_MSI_0_PEND_REG (TBD)

DEV_MSI_0_INT_EN_REG (TBD)

PWR_CTRL_REG

PWR_STAT_REG

RS232_SPD_SNS_REG

RS232_CLR_SPD_SNS_REG

178 KiB

Raw Blame History