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Blanton_TTL_Script/docs/LTC2980_channel_map.csv
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etwenandClaude Opus 5 9cc41f6fbd fix(margin): Reference VNOM to what the rails run at, and split profiles per CONN 
86 of the 144 margin channels moved up +0.8% .. +2.5% to the measured
median for this platform (3.3 -> 3.38, 0.9 -> 0.915, 0.8 -> 0.82, ...).

That is not a display change. VNOM is the denominator of margin_status'
deviation %, and it is also the basis margin_set derives high/low/OV/UV
from - so both the number you read and the voltage you apply move with
it. A rail steady at 0.756 V used to read +0.80% against a nominal 0.75
and now reads 0.00%. Margin logs from before and after cannot be
compared: the reference moved, the hardware did not.

comboA/comboB are replaced by combo_SWB_CONN13..16_{high,low}. The
per-channel percentages are positional, so they follow the rails of one
specific board - applying a CONN13 profile to a CONN16 margins the wrong
rails and nothing detects it. SWB0 and SWB1 share a profile per CONN
because their rails are identical.

Fixes two things the deletion broke:
  - margin_apply_profile_all.sh still named comboA for all nine boards,
    which would now stop at "Profile not found" nine times over. It names
    the matching per-CONN profile instead, with CB on the generic
    combo_high3, and a note that the low pass is _high -> _low.
  - docs/LTC2980_channel_map.csv is generated from settings/*.conf, so
    all 86 changed rails were stale in it. Regenerated.

The eight new profiles also still carried comboA's header comment
("alternating high/low"), which describes neither what they contain nor
what they are for.

Script A -> V1.1.3.

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_014RetWKFZFG1ZHcitQAyhwM
2026-08-30 22:13:43 +08:00

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Board,CONN,Ch,NetName,Vnom
CB,CONN13,CH0,V5P0_ALW,5.0
CB,CONN13,CH1,V3P3_ALW,3.3
CB,CONN13,CH2,PWR_VDD_MISC_ALW,0.75
CB,CONN13,CH3,V1P8_ALW,1.8
CB,CONN13,CH4,PWR_APU_VDDIO_SUS,1.1
CB,CONN13,CH5,PWR_VDD_MISC_RUN,0.75
CB,CONN13,CH6,PWR_APU_VDD_MEM_RUN,0.78
CB,CONN13,CH7,V0P8_PHY2_DVDD,0.816
CB,CONN13,CH8,V0P8_AVDD,0.8
CB,CONN13,CH9,V0P8_PHY,0.8
CB,CONN13,CH10,V1P8_FPGA,1.8
CB,CONN13,CH11,V2P5_FPGA,2.5
CB,CONN13,CH12,V1P1_FPGA,1.1
CB,CONN13,CH13,P5V_STBY,5.0
CB,CONN13,CH14,P3V3_STBY,3.3
CB,CONN13,CH15,V0P8_PHY2_AVDD,0.816
SWB0,CONN13,CH0,P0V75_DVDD_47,0.75
SWB0,CONN13,CH1,P0V75_AVDD_47,0.756
SWB0,CONN13,CH2,P1V5_AVDD_47,1.524
SWB0,CONN13,CH3,P0V9_AVDD_47,0.915
SWB0,CONN13,CH4,P1V8_1,1.816
SWB0,CONN13,CH5,PVDD3_3V_SYNTH_LDO_A3,3.38
SWB0,CONN13,CH6,PVDD3_3V_SYNTH_LDO_B1,3.38
SWB0,CONN13,CH7,P1V8_3,1.816
SWB0,CONN13,CH8,P1V8_DVDDIO_3,1.8
SWB0,CONN13,CH9,P0V75_DVDD_39,0.75
SWB0,CONN13,CH10,P0V75_AVDD_39,0.756
SWB0,CONN13,CH11,P1V5_AVDD_39,1.524
SWB0,CONN13,CH12,P0V9_AVDD_39,0.915
SWB0,CONN13,CH13,PVDD1V5_2,1.5
SWB0,CONN13,CH14,PVDD1V8_DUT,1.8
SWB0,CONN13,CH15,PVDD_MDIO,1.2
SWB0,CONN14,CH0,P0V75_AVDD_7,0.756
SWB0,CONN14,CH1,P1V5_AVDD_7,1.524
SWB0,CONN14,CH2,P0V9_AVDD_7,0.915
SWB0,CONN14,CH3,P1V8_5,1.816
SWB0,CONN14,CH4,P1V8_2,1.816
SWB0,CONN14,CH5,PVDD3_3V_SYNTH_LDO_B2,3.38
SWB0,CONN14,CH6,PVDD3_3V_SYNTH_LDO_A2,3.38
SWB0,CONN14,CH7,PVDD3_3V_SYNTH_LDO_A1,3.38
SWB0,CONN14,CH8,PVDD1V5_TSC,1.516
SWB0,CONN14,CH9,PVDD1V5_ANLG,1.516
SWB0,CONN14,CH10,NC,-
SWB0,CONN14,CH11,NC,-
SWB0,CONN14,CH12,PVDD1V5_1,1.5
SWB0,CONN14,CH13,NC,-
SWB0,CONN14,CH14,P1V8_DVDDIO_1,1.8
SWB0,CONN14,CH15,P0V75_DVDD_7,0.75
SWB0,CONN15,CH0,P1V5_AVDD_55,1.524
SWB0,CONN15,CH1,P0V9_AVDD_55,0.915
SWB0,CONN15,CH2,P0V75_DVDD_63,0.75
SWB0,CONN15,CH3,P0V75_AVDD_63,0.756
SWB0,CONN15,CH4,P1V5_AVDD_63,1.524
SWB0,CONN15,CH5,P0V9_AVDD_63,0.915
SWB0,CONN15,CH6,PVDD3_3V_SYNTH_LDO_B3,3.38
SWB0,CONN15,CH7,PVDD1V5_3,1.5
SWB0,CONN15,CH8,P0V85_STBY,0.85
SWB0,CONN15,CH9,P1V8_STBY,1.8
SWB0,CONN15,CH10,NC,-
SWB0,CONN15,CH11,P3V3_STBY,3.3
SWB0,CONN15,CH12,PVDD0V9_2,0.91
SWB0,CONN15,CH13,P0V75_DVDD_55,0.75
SWB0,CONN15,CH14,P0V75_AVDD_55,0.756
SWB0,CONN15,CH15,P1V8_DVDDIO_4,1.8
SWB0,CONN16,CH0,PVDD1V5_0,1.5
SWB0,CONN16,CH1,P1V8_4,1.816
SWB0,CONN16,CH2,PVDD3_3V_SYNTH_LDO_B5,3.38
SWB0,CONN16,CH3,PVDD3_3V_SYNTH_LDO_A5,3.38
SWB0,CONN16,CH4,PVDD3_3V_SYNTH_LDO_B4,3.38
SWB0,CONN16,CH5,PVDD3_3V_SYNTH_LDO_A4,3.38
SWB0,CONN16,CH6,P3V3,3.327
SWB0,CONN16,CH7,PVDD0_8V_T3,0.82
SWB0,CONN16,CH8,P0V75_DVDD_1,0.75
SWB0,CONN16,CH9,P0V75_AVDD_1,0.756
SWB0,CONN16,CH10,P1V5_AVDD_1,1.524
SWB0,CONN16,CH11,P0V9_AVDD_1,0.915
SWB0,CONN16,CH12,PVDD0V9_0,0.915
SWB0,CONN16,CH13,PVDD0V9_1,0.91
SWB0,CONN16,CH14,PVDD0V9_3,0.915
SWB0,CONN16,CH15,PVDD1V2_T3,1.224
SWB1,CONN13,CH0,P0V75_DVDD_47,0.75
SWB1,CONN13,CH1,P0V75_AVDD_47,0.756
SWB1,CONN13,CH2,P1V5_AVDD_47,1.524
SWB1,CONN13,CH3,P0V9_AVDD_47,0.915
SWB1,CONN13,CH4,P1V8_1,1.816
SWB1,CONN13,CH5,PVDD3_3V_SYNTH_LDO_A3,3.38
SWB1,CONN13,CH6,PVDD3_3V_SYNTH_LDO_B1,3.38
SWB1,CONN13,CH7,P1V8_3,1.816
SWB1,CONN13,CH8,P1V8_DVDDIO_3,1.8
SWB1,CONN13,CH9,P0V75_DVDD_39,0.75
SWB1,CONN13,CH10,P0V75_AVDD_39,0.756
SWB1,CONN13,CH11,P1V5_AVDD_39,1.524
SWB1,CONN13,CH12,P0V9_AVDD_39,0.915
SWB1,CONN13,CH13,PVDD1V5_2,1.5
SWB1,CONN13,CH14,PVDD1V8_DUT,1.8
SWB1,CONN13,CH15,PVDD_MDIO,1.2
SWB1,CONN14,CH0,P0V75_AVDD_7,0.756
SWB1,CONN14,CH1,P1V5_AVDD_7,1.524
SWB1,CONN14,CH2,P0V9_AVDD_7,0.915
SWB1,CONN14,CH3,P1V8_5,1.816
SWB1,CONN14,CH4,P1V8_2,1.816
SWB1,CONN14,CH5,PVDD3_3V_SYNTH_LDO_B2,3.38
SWB1,CONN14,CH6,PVDD3_3V_SYNTH_LDO_A2,3.38
SWB1,CONN14,CH7,PVDD3_3V_SYNTH_LDO_A1,3.38
SWB1,CONN14,CH8,PVDD1V5_TSC,1.516
SWB1,CONN14,CH9,PVDD1V5_ANLG,1.516
SWB1,CONN14,CH10,NC,-
SWB1,CONN14,CH11,NC,-
SWB1,CONN14,CH12,PVDD1V5_1,1.5
SWB1,CONN14,CH13,NC,-
SWB1,CONN14,CH14,P1V8_DVDDIO_1,1.8
SWB1,CONN14,CH15,P0V75_DVDD_7,0.75
SWB1,CONN15,CH0,P1V5_AVDD_55,1.524
SWB1,CONN15,CH1,P0V9_AVDD_55,0.915
SWB1,CONN15,CH2,P0V75_DVDD_63,0.75
SWB1,CONN15,CH3,P0V75_AVDD_63,0.756
SWB1,CONN15,CH4,P1V5_AVDD_63,1.524
SWB1,CONN15,CH5,P0V9_AVDD_63,0.915
SWB1,CONN15,CH6,PVDD3_3V_SYNTH_LDO_B3,3.38
SWB1,CONN15,CH7,PVDD1V5_3,1.5
SWB1,CONN15,CH8,P0V85_STBY,0.85
SWB1,CONN15,CH9,P1V8_STBY,1.8
SWB1,CONN15,CH10,NC,-
SWB1,CONN15,CH11,P3V3_STBY,3.3
SWB1,CONN15,CH12,PVDD0V9_2,0.91
SWB1,CONN15,CH13,P0V75_DVDD_55,0.75
SWB1,CONN15,CH14,P0V75_AVDD_55,0.756
SWB1,CONN15,CH15,P1V8_DVDDIO_4,1.8
SWB1,CONN16,CH0,PVDD1V5_0,1.5
SWB1,CONN16,CH1,P1V8_4,1.816
SWB1,CONN16,CH2,PVDD3_3V_SYNTH_LDO_B5,3.38
SWB1,CONN16,CH3,PVDD3_3V_SYNTH_LDO_A5,3.38
SWB1,CONN16,CH4,PVDD3_3V_SYNTH_LDO_B4,3.38
SWB1,CONN16,CH5,PVDD3_3V_SYNTH_LDO_A4,3.38
SWB1,CONN16,CH6,P3V3,3.327
SWB1,CONN16,CH7,PVDD0_8V_T3,0.82
SWB1,CONN16,CH8,P0V75_DVDD_1,0.75
SWB1,CONN16,CH9,P0V75_AVDD_1,0.756
SWB1,CONN16,CH10,P1V5_AVDD_1,1.524
SWB1,CONN16,CH11,P0V9_AVDD_1,0.915
SWB1,CONN16,CH12,PVDD0V9_0,0.915
SWB1,CONN16,CH13,PVDD0V9_1,0.91
SWB1,CONN16,CH14,PVDD0V9_3,0.915
SWB1,CONN16,CH15,PVDD1V2_T3,1.224
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