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fix(margin): Correct SWB I2C channels and LTC2977 addresses from bench

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Verified against the DUT. Two things were wrong in the SWB confs.

Channel assignment: CONN13/CONN15 and CONN14/CONN16 were paired the
wrong way round. The bench wiring is

    SWB0  Ch6 = CONN14/CONN16    Ch8 = CONN13/CONN15
    SWB1  Ch7 = CONN14/CONN16    Ch9 = CONN13/CONN15

LTC2977 addresses: the high half of each LTC2980 was recorded one step
above the low half (0x5C/0x5D, 0x62/0x63). These are 7-bit addresses
derived from 8-bit pairs, so they step by two: 0x5C/0x5E and 0x62/0x64.

This also clears the collision noted in v2.6.0, where SWB0_CONN13 chip2
and SWB0_CONN14 chip1 both landed on 0x5E on Ch6. Each channel now
carries two disjoint address pairs (0x5C/0x5E and 0x62/0x64), verified
collision-free across all eight SWB confs.

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_014RetWKFZFG1ZHcitQAyhwM
This commit is contained in:
etwen
2026-08-19 12:10:39 +08:00
co-authored by Claude Opus 5
parent a9c3dafc22
commit ababb2c3d1
8 changed files with 15 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN13.conf
+1 -1
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@@ -9,7 +9,7 @@
# --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
# it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
TRANSPORT="swb"
CB_I2C_CH=6 # CB F3 Ch6 = SWB0 CONN13/CONN14 (shared with CONN14, addr must differ)
CB_I2C_CH=8 # CB F3 Ch6 = SWB0 CONN13/CONN14 (shared with CONN14, addr must differ)
# --- I2C Configuration ---
src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN14.conf
+2 -2
View File
@@ -16,8 +16,8 @@ CB_I2C_CH=6 # CB F3 Ch6 = SWB0 CONN13/CONN14 (shared with CONN13, addr
# Format: "bus:address" (8 channels per entry / per LTC2977)
CHIPS=(
# chip1: SWB0 (CONN14)
"0:0x5E" # CH0 ~ CH7
"0:0x5F" # CH8 ~ CH15
"0:0x5C" # CH0 ~ CH7
"0:0x5E" # CH8 ~ CH15
)
# Pre-commands to run before accessing each chip (empty = none)
src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN15.conf
+1 -1
View File
@@ -17,7 +17,7 @@ CB_I2C_CH=8 # CB F3 Ch8 = SWB0 CONN15/CONN16 (shared with CONN16, addr
CHIPS=(
# chip1: SWB0 (CONN15)
"0:0x62" # CH0 ~ CH7
"0:0x63" # CH8 ~ CH15
"0:0x64" # CH8 ~ CH15
)
# Pre-commands to run before accessing each chip (empty = none)
src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN16.conf
+3 -3
View File
@@ -9,15 +9,15 @@
# --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
# it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
TRANSPORT="swb"
CB_I2C_CH=8 # CB F3 Ch8 = SWB0 CONN15/CONN16 (shared with CONN15, addr must differ)
CB_I2C_CH=6 # CB F3 Ch8 = SWB0 CONN15/CONN16 (shared with CONN15, addr must differ)
# --- I2C Configuration ---
# Format: "bus:address" (8 channels per entry / per LTC2977)
CHIPS=(
# chip1: SWB0 (CONN16)
"0:0x64" # CH0 ~ CH7
"0:0x65" # CH8 ~ CH15
"0:0x62" # CH0 ~ CH7
"0:0x64" # CH8 ~ CH15
)
# Pre-commands to run before accessing each chip (empty = none)
src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN13.conf
+2 -2
View File
@@ -9,7 +9,7 @@
# --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
# it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
TRANSPORT="swb"
CB_I2C_CH=7 # CB F3 Ch7 = SWB1 CONN13/CONN14 (shared with CONN14, addr must differ)
CB_I2C_CH=9 # CB F3 Ch7 = SWB1 CONN13/CONN14 (shared with CONN14, addr must differ)
# --- I2C Configuration ---
@@ -17,7 +17,7 @@ CB_I2C_CH=7 # CB F3 Ch7 = SWB1 CONN13/CONN14 (shared with CONN14, addr
CHIPS=(
# chip1: SWB1 (CONN13)
"1:0x5C" # CH0 ~ CH7
"1:0x5D" # CH8 ~ CH15
"1:0x5E" # CH8 ~ CH15
)
# Pre-commands to run before accessing each chip (empty = none)
src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN14.conf
+2 -2
View File
@@ -16,8 +16,8 @@ CB_I2C_CH=7 # CB F3 Ch7 = SWB1 CONN13/CONN14 (shared with CONN13, addr
# Format: "bus:address" (8 channels per entry / per LTC2977)
CHIPS=(
# chip1: SWB1 (CONN14)
"1:0x5E" # CH0 ~ CH7
"1:0x5F" # CH8 ~ CH15
"1:0x5C" # CH0 ~ CH7
"1:0x5E" # CH8 ~ CH15
)
# Pre-commands to run before accessing each chip (empty = none)
src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN15.conf
+1 -1
View File
@@ -17,7 +17,7 @@ CB_I2C_CH=9 # CB F3 Ch9 = SWB1 CONN15/CONN16 (shared with CONN16, addr
CHIPS=(
# chip1: SWB1 (CONN15)
"1:0x62" # CH0 ~ CH7
"1:0x63" # CH8 ~ CH15
"1:0x64" # CH8 ~ CH15
)
# Pre-commands to run before accessing each chip (empty = none)
src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN16.conf
+3 -3
View File
@@ -9,15 +9,15 @@
# --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
# it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
TRANSPORT="swb"
CB_I2C_CH=9 # CB F3 Ch9 = SWB1 CONN15/CONN16 (shared with CONN15, addr must differ)
CB_I2C_CH=7 # CB F3 Ch9 = SWB1 CONN15/CONN16 (shared with CONN15, addr must differ)
# --- I2C Configuration ---
# Format: "bus:address" (8 channels per entry / per LTC2977)
CHIPS=(
# chip1: SWB1 (CONN16)
"1:0x64" # CH0 ~ CH7
"1:0x65" # CH8 ~ CH15
"1:0x62" # CH0 ~ CH7
"1:0x64" # CH8 ~ CH15
)
# Pre-commands to run before accessing each chip (empty = none)