Blanton_TTL_Script

T

etwenandClaude Opus 5 ababb2c3d1 fix(margin): Correct SWB I2C channels and LTC2977 addresses from bench

Verified against the DUT. Two things were wrong in the SWB confs.

Channel assignment: CONN13/CONN15 and CONN14/CONN16 were paired the
wrong way round. The bench wiring is

    SWB0  Ch6 = CONN14/CONN16    Ch8 = CONN13/CONN15
    SWB1  Ch7 = CONN14/CONN16    Ch9 = CONN13/CONN15

LTC2977 addresses: the high half of each LTC2980 was recorded one step
above the low half (0x5C/0x5D, 0x62/0x63). These are 7-bit addresses
derived from 8-bit pairs, so they step by two: 0x5C/0x5E and 0x62/0x64.

This also clears the collision noted in v2.6.0, where SWB0_CONN13 chip2
and SWB0_CONN14 chip1 both landed on 0x5E on Ch6. Each channel now
carries two disjoint address pairs (0x5C/0x5E and 0x62/0x64), verified
collision-free across all eight SWB confs.

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_014RetWKFZFG1ZHcitQAyhwM

2026-08-19 12:10:39 +08:00

docs

docs(status): Add TTL script status sheet 20260817

2026-08-17 16:32:44 +08:00

publish

docs(arch): Add ARCHITECTURE.md and CLAUDE.md, init repo

2026-08-17 08:52:11 +08:00

secret

docs(arch): Add ARCHITECTURE.md and CLAUDE.md, init repo

2026-08-17 08:52:11 +08:00

src/Script_ABC_Blanton

fix(margin): Correct SWB I2C channels and LTC2977 addresses from bench