feat(margin): Wire SWB transport to shared cb_i2c package, bump to v2.6.0

margin.sh (swb path only, CB/i2c path untouched):
- Search blanton_cb_i2c.sh / blanton_fpga_pcimem.sh in the parent
  Blanton_Script/ dir as well; the old code only looked next to margin.sh
  where those files do not exist, so TRANSPORT=swb always failed to load.
- _swb_setup: validate CB_I2C_CH, cb_i2c_init <ch> 0x88 0x00 once per
  session, then CB_I2C_AUTO_INIT=0 to drop 4 pcimem writes per transfer.
- Probe every LTC2977 in CHIPS with cb_pmbus_read <ch> <addr> 0x00 1.
- Check cb_pmbus_read/write return codes; a NACK is now reported instead
  of silently becoming Vout=0.0000.
- Fix DEBUG_MODE collision with blanton_fpga_pcimem.sh: pcimem tracing is
  gated by MARGIN_SWB_PCIMEM_DEBUG via _swb_call.
- Add margin_swb_info / probe / scan / reset / sem wrappers.

settings: fix CB_I2C_CH per bench wiring (CONN14/CONN15 were swapped)
  Ch6 = SWB0 CONN13/14, Ch8 = SWB0 CONN15/16,
  Ch7 = SWB1 CONN13/14, Ch9 = SWB1 CONN15/16

Ref/margin_command_trace.md: new command trace reference - every i2c /
  cb_pmbus command issued by margin_init, margin_status and
  margin_apply_profile combo_high3, expanded per channel for the CB conf
  and all 8 SWB confs, with LINEAR16 values and register meanings.

Known issue documented, not changed: SWB0_CONN13 chip2 (0x5E) collides
with SWB0_CONN14 chip1 (0x5E) now that both sit on Ch6; SWB1 pattern
suggests 0x5D, pending hardware confirmation.

src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/margin.sh

@@ -5,6 +5,20 @@
 # =============================================================================
 # Version Control
 # -----------------------------------------------------------------------------
+# v2.6.0  SWB path actually wired to the shared CB I2C package. blanton_cb_i2c.sh
+#         and blanton_fpga_pcimem.sh live in the PARENT dir (Blanton_Script/), not
+#         next to margin.sh, so the backend is now searched in both places.
+#         Adds, for TRANSPORT=swb only (CB/i2c path untouched):
+#           * cb_i2c_init <ch> once in margin_init (prescale 0x88 = 100kHz) and
+#             CB_I2C_AUTO_INIT=0 afterwards -> 4 fewer pcimem writes per transfer
+#           * cb_pmbus_read presence probe of every LTC2977 in CHIPS
+#           * return-code checking on every cb_pmbus_read/write (NACK is reported
+#             instead of silently reading 0x0000)
+#           * DEBUG_MODE collision fix: blanton_fpga_pcimem.sh uses the same var
+#             name, so pcimem tracing is gated by MARGIN_SWB_PCIMEM_DEBUG
+#           * margin_swb_* wrappers (info/probe/scan/reset/sem) for debugging
+#         Physical map: CB F3 Ch6=SWB0 CONN13/14, Ch8=SWB0 CONN15/16,
+#                       Ch7=SWB1 CONN13/14, Ch9=SWB1 CONN15/16
 # v2.5.0  SWB margin support via a per-conf TRANSPORT layer. The SWB margin
 #         boards are ALSO LTC2980 (2x LTC2977) -- same chip as CB -- just reached
 #         through the CB FPGA F3 I2C master instead of a native bus. So the whole
@@ -55,6 +69,37 @@ LOG_MODE=1
 TRANSPORT="i2c"
 CB_I2C_CH=""
 
+# --- SWB transport backend (blanton_cb_i2c.sh + blanton_fpga_pcimem.sh) -------
+# The SWB margin boards' LTC2980s hang off the CB FPGA Function 3 I2C master.
+# Physical mapping (per bench wiring):
+#   CB F3 Ch6 -> SWB0 CONN13 / CONN14
+#   CB F3 Ch8 -> SWB0 CONN15 / CONN16
+#   CB F3 Ch7 -> SWB1 CONN13 / CONN14
+#   CB F3 Ch9 -> SWB1 CONN15 / CONN16
+# Two CONNs share one FPGA I2C channel, so the two boards on a channel MUST use
+# different LTC2977 slave addresses (the CHIPS array in each .conf).
+MARGIN_SWB_CHANNELS="${MARGIN_SWB_CHANNELS:-6 7 8 9}"
+# SCL prescale for cb_i2c_init: 0x88 = 100kHz, 0x24 = 400kHz (@75MHz core clk).
+MARGIN_SWB_PRESCALE_LO="${MARGIN_SWB_PRESCALE_LO:-0x88}"
+MARGIN_SWB_PRESCALE_HI="${MARGIN_SWB_PRESCALE_HI:-0x00}"
+# 0 = cb_i2c_init once in margin_init, then CB_I2C_AUTO_INIT=0 so each
+# cb_pmbus_* transfer skips the 4-register prescale/enable dance (much faster:
+# margin_status all = 32 transfers). Set 1 to keep the package default (re-init
+# on every transfer) if something else on the box reprograms the channel.
+MARGIN_SWB_AUTO_INIT="${MARGIN_SWB_AUTO_INIT:-0}"
+# 1 = grab the per-channel FPGA semaphore (cb_i2c_sem acquire) in margin_init and
+# hold it for the whole session; margin_swb_sem_release frees it. Default off so
+# margin never fails just because someone else holds it.
+MARGIN_SWB_USE_SEM="${MARGIN_SWB_USE_SEM:-0}"
+# 1 = probe every LTC2977 in CHIPS (PMBus PAGE read) at margin_init.
+MARGIN_SWB_PROBE="${MARGIN_SWB_PROBE:-1}"
+# 1 = also let blanton_fpga_pcimem.sh print every underlying pcimem command.
+# Needed because that script's debug flag is ALSO called DEBUG_MODE; margin_debug
+# would otherwise flood the console with pcimem lines.
+MARGIN_SWB_PCIMEM_DEBUG="${MARGIN_SWB_PCIMEM_DEBUG:-0}"
+_SWB_READY=0
+_SWB_SEM_HELD=0
+
 # Channel enable for margining. Rails the LTC2980 does not sequence (externally
 # enabled, e.g. an always-on MPQ8625 buck) sit with STATUS_WORD OFF=1 and won't
 # margin, because the servo DAC never soft-connects. Writing ON_OFF_CONFIG (0x02)
@@ -131,6 +176,233 @@ margin_debug() {
     echo -e "[\033[34mINFO\033[0m] DEBUG_MODE=$DEBUG_MODE"
 }
 
+# =============================================================================
+# SWB transport backend (TRANSPORT=swb only -- the CB/i2c path never gets here)
+# -----------------------------------------------------------------------------
+# Wire ops come from the shared CB I2C package:
+#   blanton_fpga_pcimem.sh -> cb_fpga <fn> <off> [data]   (PCIe BAR via pcimem)
+#   blanton_cb_i2c.sh      -> cb_i2c_init / cb_i2c_reset / cb_i2c_sem /
+#                             cb_i2c_scan / cb_pmbus_read / cb_pmbus_write
+# Both live in the parent Blanton_Script/ directory (a copy next to margin.sh is
+# also honoured if you ever bundle one).
+# =============================================================================
+
+# Locate a backend script: next to margin.sh first, then the parent dir.
+_swb_find_backend() {
+    local name="$1" p
+    for p in "$SCRIPT_DIR/$name" "$SCRIPT_DIR/../$name"; do
+        [ -f "$p" ] && { echo "$p"; return 0; }
+    done
+    return 1
+}
+
+# Source blanton_fpga_pcimem.sh (cb_fpga) + blanton_cb_i2c.sh (cb_pmbus_*).
+_swb_backend_load() {
+    local f
+    if ! declare -F cb_fpga >/dev/null 2>&1; then
+        if f=$(_swb_find_backend "blanton_fpga_pcimem.sh"); then
+            # shellcheck source=/dev/null
+            source "$f"
+            echo -e "[\033[34mINFO\033[0m] SWB backend: sourced $f"
+        else
+            echo -e "[\033[31mERRO\033[0m] blanton_fpga_pcimem.sh not found in $SCRIPT_DIR or its parent"
+            return 1
+        fi
+    fi
+    if ! declare -F cb_pmbus_read >/dev/null 2>&1; then
+        if f=$(_swb_find_backend "blanton_cb_i2c.sh"); then
+            # shellcheck source=/dev/null
+            source "$f" >/dev/null
+            echo -e "[\033[34mINFO\033[0m] SWB backend: sourced $f"
+        else
+            echo -e "[\033[31mERRO\033[0m] blanton_cb_i2c.sh not found in $SCRIPT_DIR or its parent"
+            return 1
+        fi
+    fi
+    declare -F cb_pmbus_read >/dev/null 2>&1 || {
+        echo -e "[\033[31mERRO\033[0m] cb_pmbus_read still undefined after sourcing the backend"; return 1; }
+    return 0
+}
+
+# Run a cb_* command with pcimem tracing suppressed (shared DEBUG_MODE var).
+# Echoes the command's stdout, preserves its return code.
+_swb_call() {
+    local _saved="$DEBUG_MODE" _rc
+    [ "$MARGIN_SWB_PCIMEM_DEBUG" = "1" ] || DEBUG_MODE=0
+    "$@"
+    _rc=$?
+    DEBUG_MODE="$_saved"
+    return $_rc
+}
+
+# Probe one LTC2977: 1-byte PMBus read of PAGE (0x00). Returns cb_pmbus_read's rc.
+_swb_probe_addr() {
+    _swb_call cb_pmbus_read "$CB_I2C_CH" "$1" 0x00 1 >/dev/null 2>&1
+}
+
+# --- SWB wire ops used by the transport switch below ------------------------
+# Both use _ADDR (LTC2977 7-bit slave) set by _get_chip and CB_I2C_CH from the
+# .conf. Unlike i2cset/i2cget these report failures: a NACK on the FPGA I2C
+# master used to silently turn into Vout=0.0000.
+
+# _swb_write <reg> <byte> [byte...]   -> cb_pmbus_write (LSB first for LINEAR16)
+_swb_write() {
+    local reg=$1; shift
+    [ "$DEBUG_MODE" = "1" ] && echo -e "\033[90m[DEBG] cb_pmbus_write $CB_I2C_CH $_ADDR $reg $*\033[0m"
+    if ! _swb_call cb_pmbus_write "$CB_I2C_CH" "$_ADDR" "$reg" "$@" >/dev/null 2>&1; then
+        echo -e "[\033[31mERRO\033[0m] cb_pmbus_write ch=$CB_I2C_CH $_ADDR reg=$reg failed (NACK/timeout)" >&2
+        _log_detail "ERRO cb_pmbus_write ch=$CB_I2C_CH $_ADDR $reg $*"
+        return 1
+    fi
+    return 0
+}
+
+# _swb_read_word <reg>  -> echoes "0xXXXX" parsed out of cb_pmbus_read's "=> 0xXXXX"
+_swb_read_word() {
+    local reg=$1 out word
+    [ "$DEBUG_MODE" = "1" ] && echo -e "\033[90m[DEBG] cb_pmbus_read $CB_I2C_CH $_ADDR $reg 2\033[0m" >&2
+    if ! out=$(_swb_call cb_pmbus_read "$CB_I2C_CH" "$_ADDR" "$reg" 2 2>/dev/null); then
+        echo -e "[\033[31mERRO\033[0m] cb_pmbus_read ch=$CB_I2C_CH $_ADDR reg=$reg failed (NACK/timeout)" >&2
+        _log_detail "ERRO cb_pmbus_read ch=$CB_I2C_CH $_ADDR $reg"
+        echo "0x0000"
+        return 1
+    fi
+    # cb_pmbus_read prints "  [PMB-R] ... => 0xXXXX  raw=[...] linear16=..."
+    word=$(printf '%s' "$out" | awk -F'=> ' 'NF>1{print $2}' | awk '{print $1}')
+    [[ "$word" =~ ^0[xX][0-9a-fA-F]+$ ]] || word="0x0000"
+    echo "$word"
+}
+
+# Bring up the FPGA I2C channel for this .conf: validate CB_I2C_CH, prescale +
+# enable it once (cb_i2c_init), optionally take the semaphore, then probe CHIPS.
+_swb_setup() {
+    _SWB_READY=0
+
+    if [ -z "$CB_I2C_CH" ]; then
+        echo -e "[\033[31mERRO\033[0m] TRANSPORT=swb but CB_I2C_CH is empty in the .conf"
+        return 1
+    fi
+    if ! [[ "$CB_I2C_CH" =~ ^[0-9]+$ ]] || [ "$CB_I2C_CH" -gt 17 ]; then
+        echo -e "[\033[31mERRO\033[0m] CB_I2C_CH='$CB_I2C_CH' invalid (CB F3 I2C channels are 0..17)"
+        return 1
+    fi
+    case " $MARGIN_SWB_CHANNELS " in
+        *" $CB_I2C_CH "*) ;;
+        *) echo -e "[\033[33mWARN\033[0m] CB_I2C_CH=$CB_I2C_CH is not a known SWB VRM channel ($MARGIN_SWB_CHANNELS)" ;;
+    esac
+
+    # Prescale + MOD_EN on this channel.
+    if ! _swb_call cb_i2c_init "$CB_I2C_CH" "$MARGIN_SWB_PRESCALE_LO" "$MARGIN_SWB_PRESCALE_HI"; then
+        echo -e "[\033[31mERRO\033[0m] cb_i2c_init $CB_I2C_CH failed (FPGA/pcimem access?)"
+        return 1
+    fi
+    CB_I2C_AUTO_INIT="$MARGIN_SWB_AUTO_INIT"
+    local _khz="?"; [ "$MARGIN_SWB_PRESCALE_LO" = "0x88" ] && _khz="100"
+    [ "$MARGIN_SWB_PRESCALE_LO" = "0x24" ] && _khz="400"
+    echo -e "[\033[34mINFO\033[0m] cb_i2c_init ch=$CB_I2C_CH prescale=$MARGIN_SWB_PRESCALE_LO/$MARGIN_SWB_PRESCALE_HI (~${_khz}kHz), CB_I2C_AUTO_INIT=$CB_I2C_AUTO_INIT"
+    _log "swb: cb_i2c_init ch=$CB_I2C_CH prescale=$MARGIN_SWB_PRESCALE_LO auto_init=$CB_I2C_AUTO_INIT"
+
+    if [ "$MARGIN_SWB_USE_SEM" = "1" ]; then
+        if _swb_call cb_i2c_sem "$CB_I2C_CH" acquire; then
+            _SWB_SEM_HELD=1
+        else
+            echo -e "[\033[33mWARN\033[0m] semaphore on ch=$CB_I2C_CH not acquired; continuing without it"
+        fi
+    fi
+
+    _SWB_READY=1
+
+    if [ "$MARGIN_SWB_PROBE" = "1" ]; then
+        local idx=0 chip addr bad=0
+        for chip in "${CHIPS[@]}"; do
+            IFS=':' read -r _ addr <<< "$chip"
+            if _swb_probe_addr "$addr"; then
+                echo -e "[\033[34mINFO\033[0m] probe ch=$CB_I2C_CH LTC2977[$idx] $addr : \033[32mACK\033[0m"
+            else
+                echo -e "[\033[33mWARN\033[0m] probe ch=$CB_I2C_CH LTC2977[$idx] $addr : \033[31mNACK\033[0m (wrong CB_I2C_CH / addr, board absent, or channel stuck -> margin_swb_scan / margin_swb_reset)"
+                bad=1
+            fi
+            idx=$((idx+1))
+        done
+        _log "swb: probe ch=$CB_I2C_CH chips=${CHIPS[*]} $( [ "$bad" = "0" ] && echo all-ACK || echo has-NACK )"
+    fi
+    return 0
+}
+
+# --- SWB debug / maintenance wrappers (thin shells over blanton_cb_i2c.sh) ---
+_swb_guard() {
+    if [ "$TRANSPORT" != "swb" ]; then
+        echo -e "[\033[33mWARN\033[0m] current setting is TRANSPORT=$TRANSPORT (not swb); nothing to do"
+        return 1
+    fi
+    declare -F cb_pmbus_read >/dev/null 2>&1 || { echo -e "[\033[31mERRO\033[0m] SWB backend not loaded; run margin_init first"; return 1; }
+    return 0
+}
+
+# margin_swb_info -- show the transport wiring of the loaded setting
+margin_swb_info() {
+    echo "-------------"
+    echo "[$PART_NUMBER] transport"
+    echo "-------------"
+    echo "  TRANSPORT   : $TRANSPORT"
+    if [ "$TRANSPORT" = "swb" ]; then
+        echo "  CB_I2C_CH   : $CB_I2C_CH  (CB FPGA F3, base $(printf '0x%X' $(( 0x300 + CB_I2C_CH * 0x20 ))))"
+        echo "  LTC2977     : ${CHIPS[*]}  (bus field unused on swb)"
+        echo "  prescale    : $MARGIN_SWB_PRESCALE_LO/$MARGIN_SWB_PRESCALE_HI   auto_init=$CB_I2C_AUTO_INIT   sem_held=$_SWB_SEM_HELD"
+        echo "  wire ops    : cb_pmbus_write $CB_I2C_CH <addr> 0x00 <page> / cb_pmbus_read $CB_I2C_CH <addr> 0x8b 2"
+    else
+        echo "  bus:addr    : ${CHIPS[*]}  (i2cset/i2cget)"
+    fi
+}
+
+# margin_swb_probe -- re-run the PAGE-read presence check on every LTC2977
+margin_swb_probe() {
+    _swb_guard || return 1
+    local idx=0 chip addr
+    for chip in "${CHIPS[@]}"; do
+        IFS=':' read -r _ addr <<< "$chip"
+        if _swb_probe_addr "$addr"; then
+            echo -e "  ch=$CB_I2C_CH $addr : \033[32mACK\033[0m"
+        else
+            echo -e "  ch=$CB_I2C_CH $addr : \033[31mNACK\033[0m"
+        fi
+        idx=$((idx+1))
+    done
+}
+
+# margin_swb_scan [ch] -- cb_i2c_scan on this conf's channel (0x08..0x77)
+margin_swb_scan() {
+    _swb_guard || return 1
+    _swb_call cb_i2c_scan "${1:-$CB_I2C_CH}"
+}
+
+# margin_swb_reset -- local I2C controller reset (0xD) + re-init, for a stuck bus
+margin_swb_reset() {
+    _swb_guard || return 1
+    _swb_call cb_i2c_reset "$CB_I2C_CH"
+    _swb_call cb_i2c_init "$CB_I2C_CH" "$MARGIN_SWB_PRESCALE_LO" "$MARGIN_SWB_PRESCALE_HI"
+    echo -e "[\033[34mINFO\033[0m] ch=$CB_I2C_CH reset + re-init done"
+    _log "swb: cb_i2c_reset + cb_i2c_init ch=$CB_I2C_CH"
+}
+
+# margin_swb_sem [status|acquire|release]
+margin_swb_sem() {
+    _swb_guard || return 1
+    local act="${1:-status}"
+    _swb_call cb_i2c_sem "$CB_I2C_CH" "$act"
+    case "$act" in
+        acquire) _SWB_SEM_HELD=1 ;;
+        release) _SWB_SEM_HELD=0 ;;
+    esac
+}
+
+# margin_swb_sem_release -- release the session semaphore if margin_init took it
+margin_swb_sem_release() {
+    [ "$_SWB_SEM_HELD" = "1" ] || { echo -e "[\033[34mINFO\033[0m] no semaphore held by this session"; return 0; }
+    _swb_call cb_i2c_sem "$CB_I2C_CH" release
+    _SWB_SEM_HELD=0
+}
+
 # --- Init: load setting by name ---
 margin_init() {
     if [ -z "$1" ]; then
@@ -150,15 +422,13 @@ margin_init() {
     TRANSPORT="${TRANSPORT:-i2c}"    # a blank TRANSPORT="" in a .conf means i2c
     echo -e "[\033[34mINFO\033[0m] Loaded setting: $setting_file (transport=$TRANSPORT)"
 
-    # SWB rails need the cb_pmbus_* backend; source it on demand.
+    # SWB rails need the cb_pmbus_* backend (blanton_cb_i2c.sh + blanton_fpga_pcimem.sh,
-    if [ "$TRANSPORT" = "swb" ] && ! declare -F cb_pmbus_read >/dev/null 2>&1; then
+    # normally in the parent Blanton_Script/ dir); load it and bring the FPGA I2C
-        if [ -f "$SCRIPT_DIR/blanton_cb_i2c.sh" ]; then
+    # channel up once. CB/i2c settings skip this entirely.
-            # shellcheck source=/dev/null
+    _SWB_READY=0; _SWB_SEM_HELD=0
-            source "$SCRIPT_DIR/blanton_cb_i2c.sh"
+    if [ "$TRANSPORT" = "swb" ]; then
-        else
+        _swb_backend_load || return 1
-            echo -e "[\033[31mERRO\033[0m] TRANSPORT=swb but blanton_cb_i2c.sh not found in $SCRIPT_DIR"
+        _swb_setup || return 1
-            return 1
-        fi
     fi
     _log_start_session
 }
@@ -221,8 +491,7 @@ _get_page() {
 # PAGE is written the same way on both (PMBus command 0x00).
 _open_page() {
     if [ "$TRANSPORT" = "swb" ]; then
-        [ "$DEBUG_MODE" = "1" ] && echo -e "\033[90m[DEBG] cb_pmbus_write $CB_I2C_CH $_ADDR 0x00 $1\033[0m"
+        _swb_write 0x00 "$1"
-        cb_pmbus_write "$CB_I2C_CH" "$_ADDR" 0x00 "$1" >/dev/null 2>&1
         return
     fi
     [ "$DEBUG_MODE" = "1" ] && echo -e "\033[90m[DEBG] i2cset -y $_BUS $_ADDR 0x00 $1 b\033[0m"
@@ -233,8 +502,7 @@ _open_page() {
 _i2c_write_word() {
     local reg=$1 lo=$2 hi=$3
     if [ "$TRANSPORT" = "swb" ]; then
-        [ "$DEBUG_MODE" = "1" ] && echo -e "\033[90m[DEBG] cb_pmbus_write $CB_I2C_CH $_ADDR $reg $lo $hi\033[0m"
+        _swb_write "$reg" "$lo" "$hi"
-        cb_pmbus_write "$CB_I2C_CH" "$_ADDR" "$reg" "$lo" "$hi" >/dev/null 2>&1
         return
     fi
     local word=$(( (hi << 8) | lo ))
@@ -245,8 +513,7 @@ _i2c_write_word() {
 
 _i2c_write_byte() {
     if [ "$TRANSPORT" = "swb" ]; then
-        [ "$DEBUG_MODE" = "1" ] && echo -e "\033[90m[DEBG] cb_pmbus_write $CB_I2C_CH $_ADDR $1 $2\033[0m"
+        _swb_write "$1" "$2"
-        cb_pmbus_write "$CB_I2C_CH" "$_ADDR" "$1" "$2" >/dev/null 2>&1
         return
     fi
     [ "$DEBUG_MODE" = "1" ] && echo -e "\033[90m[DEBG] i2cset -y $_BUS $_ADDR $1 $2 b\033[0m"
@@ -256,13 +523,7 @@ _i2c_write_byte() {
 # Read a 16-bit word; echoes "0xXXXX". For swb, parse cb_pmbus_read's "=> 0xXXXX".
 _i2c_read_word() {
     if [ "$TRANSPORT" = "swb" ]; then
-        [ "$DEBUG_MODE" = "1" ] && echo -e "\033[90m[DEBG] cb_pmbus_read $CB_I2C_CH $_ADDR $1 2\033[0m" >&2
+        _swb_read_word "$1"
-        local out word
-        out=$(cb_pmbus_read "$CB_I2C_CH" "$_ADDR" "$1" 2 2>/dev/null)
-        # cb_pmbus_read prints "... => 0xXXXX  raw=[...] ..."; take the word after "=>".
-        word=$(printf '%s' "$out" | awk -F'=> ' 'NF>1{print $2}' | awk '{print $1}')
-        [[ "$word" =~ ^0[xX][0-9a-fA-F]+$ ]] || word="0x0000"
-        echo "$word"
         return
     fi
     [ "$DEBUG_MODE" = "1" ] && echo -e "\033[90m[DEBG] i2cget -y $_BUS $_ADDR $1 w\033[0m" >&2

src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN13.conf

@@ -9,7 +9,7 @@
 # --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
 #     it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
 TRANSPORT="swb"
-CB_I2C_CH=6
+CB_I2C_CH=6           # CB F3 Ch6 = SWB0 CONN13/CONN14 (shared with CONN14, addr must differ)
 
 # --- I2C Configuration ---
 

src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN14.conf

@@ -9,7 +9,7 @@
 # --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
 #     it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
 TRANSPORT="swb"
-CB_I2C_CH=8
+CB_I2C_CH=6           # CB F3 Ch6 = SWB0 CONN13/CONN14 (shared with CONN13, addr must differ)
 
 # --- I2C Configuration ---
 

src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN15.conf

@@ -9,7 +9,7 @@
 # --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
 #     it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
 TRANSPORT="swb"
-CB_I2C_CH=6
+CB_I2C_CH=8           # CB F3 Ch8 = SWB0 CONN15/CONN16 (shared with CONN16, addr must differ)
 
 # --- I2C Configuration ---
 

src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB0_CONN16.conf

@@ -9,7 +9,7 @@
 # --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
 #     it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
 TRANSPORT="swb"
-CB_I2C_CH=8
+CB_I2C_CH=8           # CB F3 Ch8 = SWB0 CONN15/CONN16 (shared with CONN15, addr must differ)
 
 # --- I2C Configuration ---
 

src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN13.conf

@@ -9,7 +9,7 @@
 # --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
 #     it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
 TRANSPORT="swb"
-CB_I2C_CH=7
+CB_I2C_CH=7           # CB F3 Ch7 = SWB1 CONN13/CONN14 (shared with CONN14, addr must differ)
 
 # --- I2C Configuration ---
 

src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN14.conf

@@ -9,7 +9,7 @@
 # --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
 #     it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
 TRANSPORT="swb"
-CB_I2C_CH=9
+CB_I2C_CH=7           # CB F3 Ch7 = SWB1 CONN13/CONN14 (shared with CONN13, addr must differ)
 
 # --- I2C Configuration ---
 

src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN15.conf

@@ -9,7 +9,7 @@
 # --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
 #     it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
 TRANSPORT="swb"
-CB_I2C_CH=7
+CB_I2C_CH=9           # CB F3 Ch9 = SWB1 CONN15/CONN16 (shared with CONN16, addr must differ)
 
 # --- I2C Configuration ---
 

src/Script_ABC_Blanton/Blanton_Script/LTC2980_Margin_Script/settings/Blanton_SWB1_CONN16.conf

@@ -9,7 +9,7 @@
 # --- SWB transport (added): this LTC2980 sits behind the CB FPGA F3 I2C; reach
 #     it with cb_pmbus, not i2cset. CB_I2C_CH = FPGA I2C channel for this CONN. ---
 TRANSPORT="swb"
-CB_I2C_CH=9
+CB_I2C_CH=9           # CB F3 Ch9 = SWB1 CONN15/CONN16 (shared with CONN15, addr must differ)
 
 # --- I2C Configuration ---