etwen
cdf38a09ae
margin.sh (swb path only, CB/i2c path untouched): - Search blanton_cb_i2c.sh / blanton_fpga_pcimem.sh in the parent Blanton_Script/ dir as well; the old code only looked next to margin.sh where those files do not exist, so TRANSPORT=swb always failed to load. - _swb_setup: validate CB_I2C_CH, cb_i2c_init <ch> 0x88 0x00 once per session, then CB_I2C_AUTO_INIT=0 to drop 4 pcimem writes per transfer. - Probe every LTC2977 in CHIPS with cb_pmbus_read <ch> <addr> 0x00 1. - Check cb_pmbus_read/write return codes; a NACK is now reported instead of silently becoming Vout=0.0000. - Fix DEBUG_MODE collision with blanton_fpga_pcimem.sh: pcimem tracing is gated by MARGIN_SWB_PCIMEM_DEBUG via _swb_call. - Add margin_swb_info / probe / scan / reset / sem wrappers. settings: fix CB_I2C_CH per bench wiring (CONN14/CONN15 were swapped) Ch6 = SWB0 CONN13/14, Ch8 = SWB0 CONN15/16, Ch7 = SWB1 CONN13/14, Ch9 = SWB1 CONN15/16 Ref/margin_command_trace.md: new command trace reference - every i2c / cb_pmbus command issued by margin_init, margin_status and margin_apply_profile combo_high3, expanded per channel for the CB conf and all 8 SWB confs, with LINEAR16 values and register meanings. Known issue documented, not changed: SWB0_CONN13 chip2 (0x5E) collides with SWB0_CONN14 chip1 (0x5E) now that both sit on Ch6; SWB1 pattern suggests 0x5D, pending hardware confirmation.