etwenandClaude Opus 5.5 4ce4d6c62e feat(temp): Add DDR5 DIMM and hot-swap controller temperatures to PMON
ddr5_temp.sh reads the SPD5118 hub on each DDR5 DIMM (i2c bus 5,
0x50/0x51, register 0x31: bit[12:2], sign bit 12, 0.25 C/LSB). A failed
read prints 'read fail' instead of a number. Bus and addresses can be
passed as arguments.

hsc_temp_readback.sh reads the LTC4287 hot-swap controllers on i2c bus
28: HSC_MAIN @ 0x40 and HSC_STBY @ 0x45, internal and external sensor
each, selected through 0xF3 and read from 0x8D (Kelvin). v1.0.1 adds the
header, corrects the delay comments (DELAY is 0.5 s, not 100 ms) and
converts the file from CRLF to LF - CRLF fails outright under bash on
SONiC.

utils/setup_pmon.ttl calls both right after 'show platform temperature'.
It is shared, so every PMON snapshot gets them: Script A's baseline,
each Script B soak round, Script C, the Script 4 loop and every Script 5
check point. hsc_temp_readback.sh adds ~4 s to each snapshot.

Both are called by path and need the exec bit on the DUT.

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01UniUXkxgCG2Ty74advL8Pd
2026-09-23 14:43:28 +08:00
S
Description
Blanton Tera Term TTL reliability test
4.9 MiB
V1.2.7
Latest
2026-10-22 14:26:17 +08:00
Languages
Shell 82%
Python 18%