etwenandClaude Opus 5 8aa5c90166 docs(arch): Sync ARCHITECTURE and CLAUDE with 20260817 changes
Bring both docs in line with the five commits pulled from Gitea.

- BDF: pcimem V1.5.0 auto-detects the CB FPGA BDF, so the "edit the four
  lines per DUT" guidance was inverted. Documented the detection order
  and fpga_rescan, and flagged that utils/show_pcie_error_reg_*.ttl
  still hard-codes its 7 BDFs -- the footgun is only half gone
- Traffic: documented blanton_traffic_linespeed.sh (bcmcmd SWB loopback,
  per-pair TX/RX cross-check) and tools/bcm_mibpair_report + the three
  loopback command tables; noted the route taken differs from the
  SONiC-CLI approach Phase 4 originally planned
- Stress: stress_hhmd and stress_pcie were removed on 08-17, so the job
  count is 8 not 10; soak loop now pulls full setup_pmon (9 items)
- Constraints: added the bcmcmd exit-0 and stdin-eating gotchas
- Phases: ticked 10 completed items, corrected Phase 3/4 acceptance
  criteria, and moved BDF auto-detect out of Future Extensions

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_014RetWKFZFG1ZHcitQAyhwM
2026-08-17 21:51:17 +08:00
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Blanton Tera Term TTL reliability test
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