7937ade30eb7c2c213fe2b3120ee18a06a5cbaef
6_Blanton_Script_BER_Cycle.ttl is a standalone macro, not part of A/B/C.
Each cycle measures PRBS BER on unit 0 in the Diag OS, cold-boots into
SONiC by writing the CB FPGA, measures again, and cold-boots back; while
1, no end. The boot target is chosen in the BIOS Boot Manager ("USB
Device" = Diag, "Hard Drive" = SONiC) and confirmed by the boot
signature. The log goes to Logs\Blanton_BER_Cycle_<ts>.log.
prbsstat runs with Interval=30 and the BER is read after sleep 40. The
sleep has to be longer than the interval: checked against the error
counts 'prbs get' reports in the same cycle, sleep 10 read Diag ~60x and
SONiC ~40x low, and sleep 30 still read Diag ~60x low because its Ber is
sent 30.15 s after STArt, before the first interval is published.
Interval=30 + sleep 40 matched on both sides over 73 cycles.
Known limits: the SONiC -> Diag boot writes a hard-coded BDF
(0000:05:00.0); the prompts assume the hostname 'sonic'; the fan is set
to 30 % on the SONiC side only; the password is the placeholder.
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01UniUXkxgCG2Ty74advL8Pd
Description
Blanton Tera Term TTL reliability test
4.9 MiB